Micron Assigned Four Patents

Memory system having multiple address allocation formats
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,704,840) developed by William Radke, San Francisco, for a “memory system having multiple address allocation formats and method for use thereof.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system having multiple address allocation methods for graphics data in a computer graphics processing system. The memory system includes a plurality of memory arrays, and a format register having a programmable format flag. The status of the format flag indicates the memory address allocation format in which the memory addresses for each of the memory arrays are allocated. An address decoder is coupled to the format register to obtain the status of the format flag in order to determine the address allocation method for an array being accessed. The address decoder is further coupled to receive a requested address for a memory location in one of the memory arrays and then provide a requested memory address to the memory arrays to access. The requested address is translated by the address decoder to the requested memory address according to the memory address allocation format indicated by the format flag status for the memory array.”

The patent application was filed on July 22, 2011 (13/189,311).

Refresh of non-volatile memory cells based on fatigue conditions
Micron Technology, Boise, ID, has been assigned a patent (8,707,112) developed by three co-inventors for “refresh of non-volatile memory cells based on fatigue conditions.”

The co-inventors are Vishal Sarin, Cupertino, CA, Frankie F. Roohparvar, Monte Sereno, CA, and Jung-Sheng Hoei, Newark, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.”

The patent application was filed on Oct. 13, 2011 (13/272,407).

Replacing defective memory blocks in response to external addresses
Micron Technology, Boise, ID, has been assigned a patent (8,705,299) developed by three co-inventors for “replacing defective memory blocks in response to external addresses.”

The co-inventors are Dzung H. Nguyen, Fremont, CA, William H. Radke, Los Gatos, CA, and Vishal Sarin, Saratoga, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus has a controller. The controller is configured to address a non-defective memory block of a sequence of memory blocks in place of a defective memory block of the sequence of memory blocks such that the non-defective memory block replaces the defective memory block. The non-defective memory block is a proximate non-defective memory block following the defective memory block in the sequence of memory blocks that is available to replace the defective memory block. The controller is configured to apply a voltage-delay correction to the non-defective memory block that replaces the defective memory block based on the actual location of the non-defective memory block.”

The patent application was filed on May 15, 2013 (13/894,543).

Memory device having improved programming operation
Micron Technology, Boise, ID, has been assigned a patent (8,705,290) developed by six co-inventors for a “memory device having improved programming operation.”

The co-inventors are Krishna K. Parat, Palo Alto, CA, Prashant S. Damle, Santa Clara, CA, Kalpana Vakati, Akira Goda, Boise, ID, Alessandro Torsi, Avezzano, Italy, and Carlo Musilli, Avezzano, Italy.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.”

The patent application was filed on Sept. 15, 2012 (13/621,052).