Seagate Assigned Three Patents

Cooling a planar workpiece in evacuated environment
with dynamically moveable heat sinks
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (8,701,753) developed by Chang Bok Yi, Fremont, CA, Tatsuru Tanaka, Campbell, CA, and Paul Mcleaod, Berkeley, CA, for a “method and apparatus for cooling a planar workpiece in an evacuated environment with dynamically moveable heat sinks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus and method for cooling a planar workpiece, such as a substrate of a recording disk, in an evacuated environment has a heat exchanging structure with at least two heat sinks having substantially parallel facing surfaces disposed within a vacuum chamber. A drive arrangement is connected to the heat sinks to controllably and dynamically drive the parallel facing surfaces of the heat sinks towards and away from each other.“

The patent application was filed on May 21, 2004 (10/849,848).

Data stripes and addressing for flash memory devices
Seagate Technology, Cupertino, CA, has been assigned a patent (8,724,401) developed by four co-inventors for “data stripes and addressing for flash memory devices.”

The co-inventors are Luke William Friendshuh, Elko, MN, Mark Allen Gaertner, Vadnais Heights, MN, Jonathan Williams Haines, Boulder, CO, and Timothy Richard Feldman, Louisville, CO.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.”

The patent application was filed on Sept. 29, 2009 (12/568,729).

Addressing variations in bit error rates amongst storage segments
Seagate Technology, Cupertino, CA, has been assigned a patent (8,732,555) developed by Clifford Jayson Bringas Camalig and Mui Chong Chai, Singapore, for “addressing variations in bit error rates amongst storage segments.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosure is related to an apparatus and methods for addressing variations in bit error rates amongst data storage segments. In a particular embodiment, an apparatus includes a controller that detects variations in bit error rates amongst different segments of a plurality of segments in a storage medium. The controller also adjusts a read/write operation parameter according to the detected variations amongst the bit error rates in the plurality of segments.”

The patent application was filed on Oct. 19, 2012 (13/655,616).