SST (Microchip) Assigned Three Patents

Non-volatile memory sensing
including selective/differential threshold voltage features
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (8,693,274) developed by Hieu Van Tran, San Jose, CA, and Samar Saha, Milpitas, CA, for “systems and methods of non-volatile memory sensing including selective/differential threshold voltage features.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods are disclosed for providing selective threshold voltage characteristics via use of MOS transistors having differential threshold voltages. In one exemplary embodiment, there is provided a metal oxide semiconductor device comprising a substrate of semiconductor material having a source region, a drain region and a channel region therebetween, an insulating layer over the channel region, and a gate portion of the insulating layer. Moreover, with regard to the device, the shape of the insulating layer and/or the shape or implantation of a junction region are of varied dimension as between the gate-to-drain and gate-to-source junctions to provide differential threshold voltages between them.”

The patent application was filed on eb. 25, 2013 (13/776,690).

Operating split gate flash memory cell with coupling gate
Silicon Storage Technology, San Jose, CA, has been assigned a patent (8,711,636) developed by five co-inventors for a “method of operating a split gate flash memory cell with coupling gate.”

The co-inventors are Nhan Do, Saratoga, CA, Elizabeth A. Cuevas, Los Gatos, CA, Yuri Tkachev, Sunnyvale, CA, Mandana Tadayoni, Cupertino, CA, and Henry A. Om’Mani, Santa Clara, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.“

The patent application was filed on May 3, 2012 (13/463,558).

Mixed voltage non-volatile memory integrated circuit with power saving
Silicon Storage Technology, San Jose, CA, has been assigned a patent (8,705,282) developed by four co-inventors for a “mixed voltage non-volatile memory integrated circuit with power saving.”

The co-inventors are Hieu Van Tran, Anh Ly, Thuan Vu, San Jose, CA, and Hung Quoc Nguyen, Fremont, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An integrated circuit die has a first die pad for receiving a first voltage and a second die pad for receiving a second voltage. The second voltage is less than the first voltage. A first circuit which is operable at the first voltage is in the integrated circuit die. A second circuit which is operable at the second voltage is in the integrated circuit die and is connected to the second die pad. A circuit that detects current flow from the second die pad is in the integrated circuit die. A switch is interposed between the first die pad and the first circuit to disconnect the first die pad from the first circuit in response to current flow detected by the circuit for detecting current flow.”

The patent application was filed on Nov. 1, 2011 (13/286,969).