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OCZ (Toshiba) Assigned Two Patents

Increasing DDR memory bandwidth in DDR SDRAM, non-volatile storage devices and methods for writing data thereto

Increasing DDR memory bandwidth in DDR SDRAM
OCZ Storage Solutions, Inc., San Jose, CA, has been assigned a patent (8,688,892) developed by Ryan M. Petersen, San Jose, CA, and F. Michael Schuette, Colorado Springs, CO, for a “system and method for increasing DDR memory bandwidth in DDR SDRAM modules.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and method for increasing DDR memory bandwidth in DDR SDRAM modules are provided. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued on CAS latency before the completion of the ongoing data burst and the effect of the CAS latency is minimized in terms of the effect on bandwidth. The system and method optimizes the remaining two access latencies (t.sub.RP and t.sub.RCD) for optimal bandwidth.

The patent application was filed on Feb. 26, 2012 (13/405,350).

Non-volatile memory-based storage devices and methods for writing data thereto
OCZ Technology Group, Inc., San Jose, CA, has been assigned a patent (8,694,754) developed by Franz Michael Schuette, Colorado Springs, CO, and William Ward Clawson, Hollister, CA, for “non-volatile memory-based mass storage devices and methods for writing data thereto.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile solid state memory-based mass storage device having at least one non-volatile memory component and methods of operating the storage device. In one aspect of the invention, the one or more memory components define a memory space partitioned into user memory and over-provisioning pools based on a P/E cycle count stored in a block information record. The storage device transfers the P/E cycle count of erased blocks to a host and the host stores the P/E cycle count in a content addressable memory. During a host write to the storage device, the host issues a low P/E cycle count number as a primary address to the content addressable memory, which returns available block addresses of blocks within the over-provisioning pool as a first dimension in a multidimensional address space. Changed files are preferably updated in append mode and the previous version can be maintained for version control.

The patent application was filed on Oct. 3, 2011 (13/251,491).

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