Start-Up’s Profile: Contour Semiconductor

Company
Contour Semiconductor, Inc.

HQs
North Billerica, MA

Year founded
2000

Financial funding
Received $3.9 million in December 2007, $16 million on March 2008 and $8 million one year later, investors being Fairhaven Capital Partners, American Capital, Still River Funds, Eastward Capital Partners and private investors.

Founder and main executives

• Saul Zales, CEO since January 2014 replacing Steven Grossman, was previously founder and MD at Zales & Associates, EVP, corporate business development/strategic consultant for Fusion-io, VP and GM, corporate development, Numonyx, and director, flash memory business development, Intel, a company where he worked from 1984 to 2008.
• Dan Shepard, founder and CTO, began developing the Contour technology in the mid-1990s and formed the company in 2000. He worked formerly at Glimpse Waters, Inc., H&L Instruments, LLC, and Wellington Management. 39 patents issued and a dozen pending. He competed in the Luge World Cup and the Masters U.S. National Championships that he won in 1994.

Number of employees
Probably around 20

Technology
Low cost, high capacity, non-volatile memory addressing NAND flash market

Products description
Patented Diode Transistor Memory or DTM was invented by Shepard with simplified semiconductor fabrication process. This architecture reduces the number of mask and process steps by as much as 65% compared to NAND flash memory, according to the company adding that this results are about a three-fold improvement in capacity for the fab with a corresponding 65% reduction in wafer cost compared to NAND.

Contour explains that its non-volatile memory cell is a 4F² self-aligned structure that uses a vertical epitaxial diode as the select device.

Currently, DTM uses a phase-change material storage element.

In addition to the memory cell, the streamlined fabrication process also includes a single type of n-channel transistor and non-memory diodes used for address decoding.

Proprietary circuit techniques have been designed to optimize compatibility with existing CMOS processes.

With its cross-point array architecture, Contour’s NAND-alternative solutions support word, sector, and page-level erase commands to supplement the normal NAND flash specification, allowing improvement to system-level performance.

Latency, supposed to be like RAM, is minimized as the chip can directly access and modify any addressable location.

With phase-change material, individual cell program and erase performance is improved and write endurance has been tested for up to one billion cycles, stated Contour.

DTM offers improved write, improved write endurance, RAM-like latency and word/sector/page erase block granularity supposedly at low cost.

Roadmap
Future iterations of DTM could include magnetic or carbon nanotube storage elements.

Applications
For storage applications, such as digital photographs, movies, music, and data files, the product is suited for environments ranging from entry-level storage, the emerging Internet of Things and wearable devices to high-capacity high-performance enterprise SSDs and all non-volatile memory applications in between.

Target market
NAND flash chip

Competitors
NAND flash chip manufacturers Micron, Samsung, Toshiba/SanDisk, SK Hynix, Powerchip and several firms in phase-change memory development (see our comment.)