Hybrid Memory Cube Consortium Drives HMC Industry Adoption

The Hybrid Memory Cube Consortium (HMCC), dedicated to the development and establishment of an industry-standard interface specification for the Hybrid Memory Cube (HMC) technology, announced its continued work to build the HMC ecosystem and support for the industry adoption of this technology through the development of a new interface specification.

HMCC also released a first draft of the new specification to a list of consortium adopters that now numbers more than 120. It supports increased data rate speeds advancing short-reach (SR) performance from 10Gb/s, 12.5Gb/s, and 15Gb/s, up to 30Gb/s. It also migrates the associated channel model from SR to VSR to align with existing industry nomenclature. The ultra short-reach (USR) definition also increases performance from 10Gb/s up to 15Gb/s.

The HMCC, founded by memory providers Micron Technology, Samsung Electronics, and SK hynix, has begun circulating this draft specification to a range of adopters, with the goal of incorporating adopter members’ input and targeting a completion date of May 2014 for the final version.

The first-generation specification was completed and released publicly in April 2013; several developer and adopter companies, including Altera, Xilinx, and Open-Silicon, have already begun leveraging the specification to design products and solutions that incorporate HMC technology.

“Using the HMC Gen2 specification, designers can extract even more performance from our UltraScale FPGA architecture,” said Hugh Durdan, VP of portfolio and solutions marketing, Xilinx, Inc. “Our UltraScale devices, which are currently shipping, were designed to support this specification and offer lower risk and faster time to market for high-bandwidth applications.”

“The HMC Gen2 specification doubles the interface data rate, which enables system designers to more easily realize performance gains with next-generation 20nm and 14nm FPGAs and SoCs,” said Patrick Dorsey, senior director of product marketing, Altera Corp. “Our early start in delivering evaluation boards and the demonstrated interoperability between Hybrid Memory Cube devices and FPGAs enables customers to immediately start evaluating and developing HMC-based, high-performance systems.”

The consortium is a focused collaboration of OEMs, enablers and integrators who are codeveloping and implementing an open interface standard for HMC, a high-performance memory solution developed by Micron.

Developer members Micron Technology, Inc., Samsung Electronics Co., Ltd., Altera Corporation, ARM, IBM, Microsoft Corporation, Open-Silicon, Inc., SK hynix, Inc., and Xilinx, Inc., are working directly with adopters to support collective requirements for the creation of new markets and industry adoption of HMC.

HMC uses advanced through-silicon vias (TSVs)-vertical conduits that electrically connect a stack of individual chips-to combine high-performance logic with dynamic DRAM die. The first commercial HMC implementation is sampling from Micron in a 2GB density with 160GB/s of memory bandwidth, while using up to 70% less energy per bit than existing technologies, which lowers customers’ TCO.

HMC answers to the growing gap between the performance improvement rate of DRAM and processor data consumption rates. HMC capabilities represent a leap beyond current and near-term memory architectures in the areas of performance, packaging, and power efficiencies, offering a major shift from present memory technology.