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Silicon Storage Technology (Microchip) Assigned Two Patents

Testing data retention of non-volatile memory cell having floating gate, power line compensation for flash memory sense amplifiers

Testing data retention of non-volatile memory cell having floating gate
Silicon Storage Technology, Inc.
, San Jose, CA, has been assigned a patent (8,576,648) developed by four co-inventors for a method of “testing data retention of a non-volatile memory cell having a floating gate.”

The co-inventors are Viktor Markov, Sunnyvale, CA, Jong-Won Yoo, Cupertino, CA, Satish Bansal, Milpitas, CA, and Alexander Kotov, Sunnyvale, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method of decreasing the test time to determine data retention (e.g. leakage current) of a memory cell having a floating gate for the storage of charges thereon. The memory cell is characterized by the leakage current having a rate of leakage which is dependent upon the absolute value of the voltage of the floating gate. The memory cell is further characterized by a first erase voltage and a first programming voltage, applied during normal operation, and a first read current detected during normal operation. The method applies a voltage greater than the first erase voltage or greater than the first programming voltage, to over erase the floating gate. The memory cell including the floating gate is subject to a single high temperature bake. The memory cell is then tested for data retention of the floating gate based on the single high temperature bake.”

The patent application was filed on Nov. 9, 2011 (13/293,056).

Power line compensation for flash memory sense amplifiers
Silicon Storage Technology, San Jose, CA, has been assigned a patent (8,565,038) developed by Hieu Van Tran, San Jose, CA, for a “memory system that compensates for power level variations in sense amplifiers for multilevel memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.”

The patent application was filed on April 23, 2010 (12/766,682).

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