SanDisk Assigned Four Patents

P-type control gate in non-volatile storage and methods for forming same
SanDisk Technologies, Plano, TX, has been assigned a patent (8,546,214) developed by seven co-inventors for a “P-type control gate in non-volatile storage and methods for forming same.”

The co-inventors are Takashi Whitney Orimoto, Sunnyvale, CA, Atsushi Suyama, Naoya, Japan, Ming Tian, Yokkaichi, Japan, Henry Chin, Santa Clara, CA, Henry Chien, San Jose, CA, Vinod Robert Purayath, Santa Clara, CA, and Dana Lee, Saratoga, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon.”

The patent application was filed on Sept. 21, 2010 (12/887,328).

Memory cell that includes a carbon-based reversible resistance switching element
compatible with steering element, and methods of forming same
SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (8,551,855) developed by Huiwen Xu, Sunnyvale, CA, Er-Xuan Ping, Fremont, CA, and Xiying Costa, San Jose, CA, for “memory cell that includes a carbon-based reversible resistance switching element compatible with a steering element, and methods of forming the same.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory cells, and methods of forming such memory cells, are provided that include a steering element coupled to a carbon-based reversible resistivity switching material that has an increased resistivity, and a switching current that is less than a maximum current capability of the steering element used to control current flow through the carbon-based reversible resistivity switching material. In particular embodiments, methods and apparatus in accordance with this invention form a steering element, such as a diode, having a first width, coupled to a reversible resistivity switching material, such as aC, having a second width smaller than the first width.”

The patent application was filed on July 13, 2010 (12/834,942).

Non-volatile storage with substrate cut-out and process of fabricating
SanDisk Technologies, Plano, TX, has been assigned a patent (8,551,839) developed by Masaaki Higashitani, Cupertino, CA, for “non-volatile storage with substrate cut-out and process of fabricating.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Shallow trench isolation regions are positioned between NAND strings (or other types of non-volatile storage). These isolation regions include sections that form concave cut-out shapes in the substrate for the NAND string (or other types of non-volatile storage). The floating gates (or other charge storage devices) of the NAND strings hang over the sections of the isolation region that form the concave cut-out shape in the substrate. To manufacture such a structure, a two step etching process is used to form the isolation regions. In the first step, isotropic etching is used to remove substrate material in multiple directions, including removing substrate material underneath the floating gates. In the second step, anisotropic etching is used to create the lower part of the isolation region. ”

The patent application was filed on March 9, 2011 (13/043,980).

On chip dynamic read for non-volatile storage
SanDisk Technologies, Plano, TX, has been assigned a patent (8,576,624) developed by Deepanshu Dutta, San Jose, CA, Dana Lee, Saratoga, CA, and Jeffrey Lutze, San Jose, CA, for an “on chip dynamic read for non-volatile storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.”

The patent application was filed on Feb. 5, 2013 (13/759,700).