Silicon Storage Technology (Microchip) Assigned Three Patents

Non-volatile memory systems
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (8,432,750) developed by Hieu Van Tran, San Jose, CA, and Sakhawat M. Khan, Atherton, CA, for "non-volatile memory systems and methods including page read and/or configuration features."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described."

The patent application was filed on Dec. 6, 2010 (12/961,458).

FIN-FET non-volatile memory cell,
and array and method of manufacturing
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (8,461,640) developed by Yaw Wen Hu, Cupertino, CA, and Prateep Tuntasood, San Jose, CA, for a "FIN-FET non-volatile memory cell, and an array and method of manufacturing."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A non-volatile memory cell has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the top surface and the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is insulated from the top surface and is capacitively coupled to the two side surfaces of a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An erase gate is insulated from the second region and is adjacent to the floating gate and coupling gate."

The patent application was filed on Sept. 8, 2009 (12/555,756).

Sub volt flash memory system
Silicon Storage Technology, Inc., San Jose, CA, has been assigned a patent (8,456,904) developed by four co-inventors for a "sub volt flash memory system."

The co-inventors are Hieu Van Tran, San Jose, CA, Sang T. Nguyen, Union City, CA, Anh Ly, San Jose, CA, and Hung Q. Nguyen, Fremont, CA.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage or ground and other MOS transistors have a bulk voltage that is different. The bulk voltage may be set to forward or reverse bias pn junctions in the MOS transistor. The various circuits include comparators, operational amplifiers, sensing circuits, decoding circuits and the other circuits. The circuits may be included in a memory system."

The patent application was filed on June 29, 2011 (13/172,599).