PLDA With IP-Maker
Integrating PCIe 3.0 controller with NVM Express IP core for SSDs
This is a Press Release edited by StorageNewsletter.com on June 6, 2013 at 3:07 pmPLDA, in PCIe and interface IP solutions, and IP-Maker announced a joint solution integrating itss XpressRICH3 PCIe 3.0 with IP-Maker’s NVM Express (NVMe) IP cores.
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Cloud computing, video broadcast and HPC applications require high bandwith and low latency storage devices such as PCIe SSDs, enabled by the combination of speed and performance provided by PCIe 3.0 and NVMe protocol.
The integration of the XpressRICH3 PCIe 3.0 controller for ASIC and the hardware optimized NVMe IP core delivers performance, featuring low latency and high data transfer rates. This integrated PCIe with NVMe available for both ASIC designs and FPGA prototyping of ASIC designs will help customers accelerate their system level development and validation, and reduce the risk. It also offloads CPU and OS, resulting in a better server power footprint.
"We are pleased to work with IP-Maker to satisfy demand in this innovative market segment. We believe that the integration of PCIe 3.0 into SSDs along with an NVM Express protocol will be the most powerful and efficient solution for performance computing needs," said Stephane Hauradou, CTO for PLDA.
"Our mutual customers will benefit from a fully validated solution, helping to reduce time-to-market thanks to faster system integration," said Mickael Guyard, product marketing director, IP-Maker. "The integration of NVMe IP core with the PLDA PCIe 3.0 controller will deliver the outstanding performance required by customers today."
PLDA XpressRICH3 for ASIC Spec
PLDA PCIe 3.0 (XpressRICH3) is a performance, configurable PCIe endpoint, root port, and switch semiconductor IP compliant to the PCIe rev.3.0 specification. It inherits the architecture performance and reliability of PLDA’s previous generations of PCIe interface IP and provides advanced features and configurability.
IP-Maker NVMe
It is a data transfer manager to be integrated in the PCIe SSD controller between the PCIe communication interface and the NAND flash controller, therefore off-loading the host CPU. It is NVM Express 1.0d compliant.











