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Avery Design Announced eMMC and SD Verification IPs

Developed in SystemVerilog

Avery Design Systems, Inc., in functional verification productivity solutions, announced availability of its eMMC and SD verification IPs.

The addition of eMMC and SD/SDIO extends Avery’s portfolio of storage-related VIP which also includes Universal Flash Storage (UFS), SCSI Express (SOP/PQI), NVM Express, USB Attached SCSI (UASP), and SATA.

eMMC-Xactor supports eMMC 4.5.1 and draft 5.0 standards work by JEDEC targeting high performance embedded flash memory systems. SD-Xactor supports SD/SDIO 4.0 for high performance memory cards, systems, and IO peripherals.

eMMC-Xactor and SD-Xactor are complete verification solutions enabling design and verification engineers to quickly and extensively test the functionality of memory systems.

The VIPs include:

  • Host and Device BFMs
  • Producer-consumer scoreboard
  • Compliance testsuite
  • Protocol checks
  • Protocol analyzer tracker
  • Functional coverage model

Models and compliance test suites are developed in SystemVerilog and support UVM, OVM, and VMM environments.

"Avery is focused on delivering industry leading VIP for the accelerating mobile memory revolution," says Chilai Huang, president of Avery Design. "Our solution enables designers to thoroughly verify their designs functionally adhere to the latest standards and effectively pinpoint areas of non-compliance or performance bottlenecks."

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