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Spansion Assigned Two Patents

Nonvolatile storage area, memory cell regions

Semiconductor device and method for controlling thereof

Spansion, Inc., Sunnyvale, CA, has been assigned a patent (8,423,705) developed by six co-inventors for a "semiconductor device and method for controlling thereof."

The co-inventors are Hirokazu Nagashima, Kazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, and Kenichi Takehana, Kawasaki, Japan.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information."

The patent application was filed on June 13, 2008 (12/139,274).

Storage device, control method of storage device,
and control method of storage control device

Spansion, Inc., Sunnyvale, CA, has been assigned a patent (8,395,959) developed by Masahiro Niimi, Aichi-ken, Japan, for a "storage device, control method of storage device, and control method of storage control device."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Memory cell regions as units of erasing operation are sectors S, and units of reading operation and/or writing operation are blocks B0 to B3 in a sector, in which a block address BA for selecting one of blocks B0 to B3 is held in block address buffer (BAB) 3. Holding operation is executed prior to reading or writing operation, and hence in subsequent reading operation or writing operation, re-input is not needed. Depending on the held block address BA, any one of selection signals YDn (n=0 to 3) is selected, and any one block is selected depending on the selection signal YDn. This state is maintained until the block address BA held in the block address buffer (BAB) 3 is rewritten, and therefore it is not required to enter or decode the block address BA on every occasion of reading and/or writing operation, so that the access operation can be executed promptly and at low current consumption."

The patent application was filed on Aug. 25, 2006 (11/510,061).

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