WD Assigned Four Patents

High performance command processing in SSDs

Western Digital Technologies, Inc. Irvine, CA, has been assigned a patent (8,423,722) developed by Marvin R. Deforest, Niwot, CO, Matthew Call, Longmont, CO, and Mei-Man L. Syu, Fremont, CA, for a "system and method for high performance command processing in SSDs."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "SSDs can yield very high performance if it is designed properly. A SSD typically includes both a front end that interfaces with the host and a back end that interfaces with the flash media. Typically SSDs include flash media that is designed with a high degree of parallelism that can support a very high bandwidth on input/output (I/O). A SSD front end designed according to a traditional HDD model will not be able to take advantage of the high performance offered by the typical flash media. Embodiments of the invention provide improved management of multiple I/O threads that take advantage of the high performing and concurrent nature of the back end media, so the resulting storage system can achieve a very high performance."

The patent application was filed on Aug. 26, 2011 (13/219,555).

Hybrid drive storing copy of data
in non-volatile semiconductor memory
for suspect disk data sectors

Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (8,427,771) developed by Chun Sei Tsai, Tustin, CA, for a "hybrid drive storing copy of data in non-volatile semiconductor memory for suspect disk data sectors."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM) comprising a plurality of memory segments. A read command is received from a host to read data from a first data sector. Data is read from the first data sector during a first read operation and a determination is made as to whether the first data sector is suspect. When the first data sector is suspect, the data is written to a first memory segment of the NVSM."

The patent application was filed on Oct. 21, 2010 (12/909,695).

HDD head stack assembly having laminar FPC
with conductive bump extending
to second conductive layer

Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (8,422,171) developed by Albert J. Guerini, Gilroy, CA, for a "disk drive head stack assembly having a laminar flexible printed circuit with a conductive bump extending to a second conductive layer."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A disk drive head stack assembly includes a laminar flexible printed circuit (FPC) having first and second conductive layers, with a dielectric layer between. An integrated circuit chip is mounted to the laminar FPC. The IC chip may have a first plurality of terminals closer to the first conductive layer than to the second conductive layer, and second plurality of terminals that is offset towards the second conductive layer relative to the first plurality of terminals. First and second pluralities of conductive bumps contact and connect conductive traces of the first and second conductive layers to the first and second plurality of terminals, respectively. An average height of the second plurality of conductive bumps may be greater than that of the first plurality of conductive bumps. The second plurality of conductive bumps is aligned with and passes through a plurality of openings through the dielectric layer."

The patent application was filed on Feb. 24, 2012 (13/405,038).

Storage device employing data path protection
using both LBA and PBA

Western Digital Technologies, Inc., Irvine, CA, has been assigned a patent (8,397,107) developed by Mei-Man L. Syu, Fremont, CA, and William B. Boyle, Lake Forest, CA, for a "storage device employing data path protection using both LBA and PBA."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A storage device is disclosed comprising a non-volatile memory including a plurality of memory segments. A write command is received comprising a logical block address (LBA) and user data. The LBA is mapped to a physical block address (PBA) for addressing one of the memory segments. First error code redundancy is generated in response to the LBA, and second error code redundancy in response to the PBA. User data and the first and second error code redundancy are written to the memory segment addressed by the PBA."

The patent application was filed on Dec. 11, 2009 (12/636,614).