Freescale Assigned Two Patents

Non-volatile storage alteration tracking

Freescale Semiconductor, Inc., Austin, TX, has been assigned a patent (8,380,918) developed by Richard Soja, James B. Eifert,and Timothy J. Strauss, Austin, TX, for a "non-volatile storage alteration tracking."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for tracking alteration of a non-volatile storage includes receiving a request to modify a tracked region of the non-volatile storage. In response to the request, it is determined whether or not a modification of data stored in a non-erasable one-time programmable (NEOTP) alteration log region has occurred. In response to determining that the modification of the data stored in the NEOTP alteration log region has occurred, the tracked region of non-volatile storage is modified in response to the request. In response to determining that the modification of the data stored in the NEOTP alteration log region has not occurred, the request to modify the tracked region of the non-volatile memory is denied."

The patent application was filed on Jan. 7, 2010 (12/683,549).

Non-volatile memory and logic circuit process integration

Freescale Semiconductor, Austin, TX, has been assigned a patent (8,389,365) developed by Mehul D. Shroff, and Mark D. Hall, Austin, TX, for a "non-volatile memory and logic circuit process integration."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material."

The patent application was filed on March 31, 2011 (13/077,501).