Intel Assigned Two Patents

Network storage target boot and network connectivity
through common network device

Intel Corp., Santa Clara, CA, has been assigned a patent (8,341,392) developed by David M. Lerner, Hillsboro, OR, Dave Matheny, Cedar Park, TX, and Douglas D. Boom, Portland, OR, for a "network storage target boot and network connectivity through a common network device."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network device driver is loaded during a machine boot, where the bus-to-network device driver is capable of sending machine bus commands over a network, providing access to the network for a network device driver, and distinguishing between received responses to the machine bus commands and other network traffic corresponding to the network device driver. Loading of the bus-to-network device driver can occur in response to an OS load of bus drivers. For example, the bus-to-network device driver can be an iSCSI driver, and the OS load of bus drivers can be the OS load of SCSI drivers."

The patent application was filed on May 16, 2012 (13/473,288).

Mirroring data between redundant storage controllers
of storage system

Intel Corp., Santa Clara, CA, has been assigned a patent (8,375,184) developed by five co-inventors for a "mirroring data between redundant storage controllers of a storage system."

The co-inventors are Pankaj Kumar, Chandler, AZ, Hang T. Nguyen, Tempe, AZ, Mark Yarch, Timothy J. Jehl, Chandler, AZ, and John A. Miller, Hillsboro, OR.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed."

The patent application was filed on Nov. 30, 2009 (12/627,440).