Everspin Revealing 1Mb Serial MRAM With Quad SPI Interface

Everspin Technologies, Inc. announced the MR10Q010, a 1-Megabit serial MRAM with a Quad SPI interface.

Quad SPI, which has four serial I/O paths, is an evolutionary upgrade from SPI, which had one serial I/O path. The combination of Quad SPI with MRAM allows users to take advantage of high write speeds with no write delay as experienced with flash or EEPROM based products. Everspin expects the new part, which has a 104MHz clock speed with 52MBps read/write bandwidth, to be used in applications that require high frequency, high-performance writes of most critical data. The MR10Q010 delivers all the benefits of Everspin Magnetic RAM (MRAM) – the fast non-volatile random access memory – with reliability.
 
"By supporting the Quad SPI interface, Everspin continues to expand the reach of its MRAM products," said Gregory Wong, analyst at Forward Insights. "The Quad SPI interface provides designers more options to realize high-performance systems with MRAM technology."
 
The Quad SPI interface is primarily used in the industry to reduce pin count, save board space, and reduce design complexity. SPI and Quad SPI are widely used in microprocessors for most embedded computing applications. The MR10Q010 MRAM offers read/write bandwidth comparable to parallel I/O MRAM but with a savings in pins and allows execute in place (XIP) operation.
 
Because it is MRAM, the MR10Q010 can perform writes faster than flash or EEPROM. Fast writes are critical for data-intensive or data logging applications with frequent writing, such as capturing metadata in storage, environmental data in metering, or journal memory in RAID systems.
 
"Everspin continues to innovate and enhance its MRAM products. Our support for Quad SPI will help to proliferate our products into new and high volume markets," said Phill LoPresti, president and CEO of Everspin.
 
The MR10Q010 includes a complete command set for Quad SPI operations including fast reads and writes in which address and data are input on all four I/Os to reduce clock cycles. The part comes in a cost-effective, low pin count 16-pin SOIC package – a savings of 20 pins over parallel interfaces – that supports low voltage levels with separate VDDQ for I/O. It is compatible with future high-density Quad SPI packages that Everspin is planning to introduce.
 
Engineering samples will be available in the second quarter of 2013.