OCZ Assigned Two Patents

Reducing write cycles in NAND-based flash memory devices

OCZ Technology Group, Inc., San Jose, CA, has been assigned a patent (8,375,162) developed by William J. Allen, Cupertino, CA, and Franz Michael Schuette, Colorado Springs, CO, for a "method and apparatus for reducing write cycles in NAND-based flash memory devices."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A NAND-based flash memory device and a method of its operation that extends the life of the device by reducing the number of unnecessary write cycles to the device. The memory device includes blocks, pages contained by each of the blocks, and a page abstraction layer containing a look-up table for translating logical page numbers into physical page numbers. A certain number of the pages in at least one of the blocks is preferably reserved so as not to be used in default data storage mode but instead used to shuffle data within the at least one block using a dynamic page address scheme, whereby data are dynamically moved from one page to an empty page in the same block using dynamic page mapping."

The patent application was filed on June 3, 2010 (12/793,023).

Mass storage device and method
for offline background scrubbing
of solid-state memory devices

OCZ Technology Group, Inc., San Jose, CA, has been assigned a patent (8,370,720) developed by William J. Allen, Cupertino, CA, for a "mass storage device and method for offline background scrubbing of solid-state memory devices."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A solid-state mass storage device and method for its operation that includes performing preemptive scrubbing of data during offline periods or disconnects from a host system to which the mass storage device is attached. The device includes a system interface adapted to connect the drive to a host system, at least one nonvolatile memory device, controller means through which data pass when being written to and read from the memory device, a volatile memory cache, a system logic device, and an integrated power source for powering the drive. The system logic device is configured to operate when the drive is not functionally connected to a host system, execute copy commands without accessing a host system, and prioritize preemptive scrubbing of addresses in the memory device on the basis of risk of data loss based on one or more parameters logged by the internal system logic device."

The patent application was filed on Aug. 19, 2010 (12/859,595).