SanDisk Assigned Three Patents

Flash memory cell arrays having dual control gates
per memory cell charge storage element

SanDisk Technologies, Inc., Plano, TX, has been assigned a patent (8,334,180) developed by Eliyahou Harari, Saratoga, CA, for a "flash memory cell arrays having dual control gates per memory cell charge storage element."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers."

The patent application was filed on Aug. 5, 2011 (13/204,533).

Bit-line connections for non-volatile storage

SanDisk Technologies, Inc., Plano, TX, has been assigned a patent (8,325,529) developed by Chen-Che Huang, Campbell, CA, Chun-Ming Wang, Fremont, CA, and Masaaki Higashitani, Cupertino, CA, for a "bit-line connections for non-volatile storage."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad."

The patent application was filed on June 10, 2010 (12/813,437).

Memory system with sectional data lines

SanDisk 3D, Milpitas, CA, has been assigned a patent (8,358,528) developed by Tianhong Yan, San Jose, CA, and Luca Fasoli, Campbell, CA, for "memory system with sectional data lines."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay."

The patent application was filed on April 4, 2011 (13/079,613).