eASIC and Proton Together for LDPC NAND Flash Read Channel

eASIC Corporation, provider of ASICs devices, and Proton Digital Systems, Inc., provider of flash memory reliability IP solutions, announced the availability of an LDPC (Low Density Parity Check) NAND flash read channel for enterprise storage applications.

The combination of IP from Proton Digital Systems and eASIC’s new ASIC devices enables enterprise storage vendors to double the throughput performance at approximately half the power that can be achieved using FPGAs.

The Proton Digital Systems LDPC read channel enables enterprise flash storage system companies to leverage low cost MLC flash devices and increase the longevity of the flash to 45,000 program/erase cycles, compared to only 5,000 program/erase cycles with traditional BCH algorithms. This essentially extends the operating lifetime of the enterprise storage system to 10 years.

"We were keen to work with eASIC as we are increasingly seeing eASIC devices being selected as platforms for enterprise grade customized flash controllers," said Dr. Andrei Vityaev, CEO at Proton Digital. "In enterprise storage systems, production volumes are often not high enough and the market changes are too dynamic to justify cell-based ASICs but performance and low power requirements are beyond the capability of FPGAs. This makes an eASIC FLASH controller solution ideal for this space."

"Proton’s flash Reliability IP suite is well proven to meet the demands posed by the latest dense NAND FLASH memory geometries," said Jasbinder Bhoot, VP of marketing at eASIC Corporation.

"Robust LDPC-based error correction with soft data collection and signal processing is going to be a must in the enterprise storage space as OEMs strive to increase system endurance while reducing cost by using cheaper NAND flash memory," added Bhoot. "The eASIC solution is gaining traction in this fast evolving market as the eASIC configurable logic fabric enables fast time to market for a controller optimized for a particular flash node. At the same time the power and performance advantages over FPGA make this approach very compelling."

LDPC Read Channel includes the following deliverables:

Set of Flash-optimized LDPC codes
Synthesizable Verilog code with synthesis and simulation scripts
Integration test bench and tests
Firmware routines
Complete reference design system for flash reliability testing with LDPC Read Channel