Talino Architecture for Enterprise SSDs by BiTMICRO

BiTMICRO Networks, Inc. revealed its next-generation SSD Talino ASIC Architecture.

This two-tier architecture will be the basis for the company’s upcoming maxIO line of I/O accelerators and SSDs.

The architecture begins with their Talino Quad Core ASIC controller, which integrates embedded processors with a high speed multi-bus design to achieve performance. A single controller can reach up to 400,000 random IOPS at 4KB and can perform up to 4,096 concurrent flash operations. To complete the architecture, the Talino controller connects with several of BiTMICRO’s new ISIP ASICs.

"One of the innovative attributes of the Talino architecture is its ‘building block’ design. A single Talino ASIC can connect to as many as 60 ISIP chips, each connecting to up to eight flash die," states Zophar Sante, VP of marketing and sales, "Multiple Talino ASICs can easily interconnect via a PCIe switch to create 1U, 2U and 3U complete storage systems with enormous capacities and blistering performance. These Talino based storage systems can use "off the shelf" front-end file systems that support FC, FCoE, iSCSI, NFS, CIFS, Ethernet and can also include volume management, virtualization and storage services software."

The company has created an architecture that surpasses traditional enterprise standards, while incorporating popular military-grade features from its other product lines. The end result is an architecture that creates a new class of solid state products for the enterprise storage market.

"The technology we put into our Talino Architecture puts BiTMICRO far beyond what anyone else is doing with solid state storage," says Rey Bruce, CEO. "In terms of performance, scalability, and reliability, there’s no other architecture that can match what Talino can deliver. And we will continue the innovation of Talino so it will remain cutting edge for years to come."

The Talino ASIC packs in more features, with multiple high performance buses specifically built for flash memory, XOR RAID, power management features, AES-XTS encryption, end-to-end protection information, and data path protection.

The Talino ASIC is also versatile. Interface controllers are built directly into the chip, with 8x 5Gb PCIe lanes, 2x 6Gb SAS ports and 2x 6Gb SATA ports.

With two ISIP embedded directly into the controller, Talino can be integrated in a single-tier architecture while incorporating ISIP’s features. ISIP itself includes hot plug support, RAID configuration support and powerful BCH error correction code. The chip supports Legacy, Toggle 1.0 and ONFI 2.3 flash in single, dual, quad, and octal die packages.

BiTMICRO’s initial maxIO product line will use the Talino Architecture and is expected to include PCIe, NVMe and SAS interfaces.