Micron Assigned Three Patents

Data conditioning to improve flash memory reliability

Micron Technology, Inc., Boise, ID, has been assigned a patent (8,281,061) developed by William H. Radke, Los Gatos, CA, Vishal Sarin, Cupertino, CA, and Jung-Sheng Hoei, Newark, CA, for a "data conditioning to improve flash memory reliability."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed."

The patent application was filed on March 31, 2008 (12/059,831).

Semiconductor constructions
for transistor gates and NAND cell units

Micron Technology, Inc., Boise, ID, has been assigned a patent (8,288,817) developed by Yongjun Jeff Hu, Boise, ID, for a "semiconductor constructions for transistor gates and NAND cell units."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures."

The patent application was filed on Jan. 7, 2011 (12/986,487).

Semiconductor memory cell and array
using punch-through to program and read same

Micron Technology, Inc., Boise, ID, has been assigned a patent (8,295,078) developed by Serguei Okhonin, Lausanne, Switzerland, and Mikhail Nagoga, Pully, Switzerland, for a "semiconductor memory cell and array using punch-through to program and read same."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate."

The patent application was filed on April 22, 2011 (13/092,704).