Silicon Storage Technology Assigned Patent

Silicon Storage Technology, Inc., San Jose, CA has been assigned a patent (8,270,213) developed by eight co-inventors for a "flash memory array system including a top gate memory cell."

The co-inventors are Hieu Van Tran, San Jose, CA, Hung Quoc Nguyen, Fremont, CA, Anh Ly, San Jose, CA, Sheng-Hsiung Hsueh, San Jose, CA, Sang Thanh Nguyen, Union City, CA, Loc B. Hoang, San Jose, CA, Steve Choi, Irvine, CA, and Thuan T. Vu, San Jose, CA

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included."

The patent application was filed on Dec. 7, 2010 (12/962,343).