Texas Memory Awarded Two U.S. Patents

Texas Memory Systems Inc. has been awarded two patents by the U.S. Patent Office for techniques it developed to increase reliability within its systems and for the Flash media used with its devices.

"The awarding of these two patents proves that we are not only the most experienced player in the solid state storage industry today but that we remain one of the most innovative," said Jamon Bowen, Director of Sales Engineering at Texas Memory Systems. "By continuing to develop techniques that improve the reliability of our systems and the media used within them, we are extending our commitment to customers that they can trust Texas Memory Systems and the RamSan product line to accelerate their most critical applications." 

The first patent (Patent No. 7,928,791 – Method and apparatus for clock calibration in a clocked digital device) increases the reliability of the RamSan systems by providing predictable performance for a wide range of integrated circuit devices, including Field Programmable Gate Arrays (FPGA) and Application-specified integrated cirucuits (ASIC). FPGAs play an essential role in Texas Memory Systems’ high-performance solutions that are delivered with its highly parallel architecture.

As the number of integrated circuit devices inside a system increases, so does the need to tune the timing requirements of every clock cycle rather than using a one-size-fits-all approach. This patent allows Texas Memory Systems to fine tune its calibration of the timing requirements on every clock cycle to increase the reliability of the system.

"Input and output timing characteristics for integrated circuits depend heavily upon variations in device processing parameters, as well as upon changes in device operating voltage and temperature," said Charles Camp, CTO at Texas Memory Systems. "Typical approaches for mitigating these effects often rely on complicated techniques and the use of redundant signaling information. This patent offers a significant improvement over these approaches by relying solely on the clock signal itself to establish stable input and output characteristics across wide variations in process, voltage and temperature."

The second patent (Patent No. 7,818,525 – Efficient reduction of read disturb errors in NAND Flash memory) relates to a way in which Texas Memory Systems prevents ‘read disturb’ errors. These are events that occur when many read cycles are performed on a block within a Flash chip resulting in a buildup of voltage in nearby blocks, which can result in data corruption due to changes in the programmed status. Flash manufacturers acknowledge that disturb failures occur on their devices, which can compromise the integrity of the data.  

Texas Memory Systems’ patented technique initiates an action that moves the data once the number of ‘reads’ performed on a particular section of data has reached a specified count threshold. This action removes the built up voltage and returns the data to an uncompromised state. This action ensures reliability of the data stored on a Texas Memory Systems’ devices.