Macronix Develops 3D NAND Flash Technology

Macronix International Co., Ltd., provider of non-volatile memory semiconductor solutions, announced its research results that provide a path to the most scalable and most efficient 3D NAND Flash using its patented BE- SONOS (barrier engineering) charge-trapping technology and 3D decoding architecture. This Macronix’s work addressing 3D NAND Flash has been chosen as one of the 8 highlight papers by the 2010 Symposium on VLSI Technology.

In this paper, Macronix reports the fabrication and demonstration of an 8-layer, 75nm half-pitch, 3D VG (Vertical Gate) NAND Flash using a junction-free BE-SONOS device. The BE-SONOS charge-trapping device provides both high reliability and simple structure suitable for 3D. At an equivalent 0.0014 (um) 2 cell size (near world record), Macronix’s 3D VG NAND has shown no Z-directional interference, large read current, and large program window (7V) for MLC (Multi-level Cell) operation.

"Traditional NAND Flash will be facing technology barrier when it scales to below 2Xnm node," said C. Y. Lu, President of Macronix. "The three-dimensional memory cell array structure has been proposed to be the most promising candidate for NAND Flash to shrink to below 1Xnm. Macronix’s 3D memory research results based on our own BE-SONOS technology have set a new milestone for next generation NAND Flash to meet high density capacity requirement."

The 3D cell technology stacks memory cells in three dimensions, thus provides an important solution to making terabit NAND Flash possible. Using 3D stacking, NAND Flash may achieve higher data storage capacity and effectively lower fabrication cost without relying on advances in lithography technology. Therefore, some memory manufacturers have invested in 3D research recently.

Several 3D NAND Flash structures have been proposed, such as P-BiCS (Pipe-shaped Bit Cost Scalable), TCAT (Terabit Cell Array Transistor), VSAT (Vertical Stacked Array Transistor) and VG (Vertical Gate). However, in a 3D structure interference (cross talk) occurs not only between neighboring cells in the same plane but also between vertical neighbors in adjacent planes. This has become a new challenge in addition to the conventional Moore’s law scaling issues.

Through detailed analyses on scalability, reading current (which determines read speed performance) and cross talk, Macronix’s work has chosen the VG architecture, believing it is the best approach. Simulation shows this structure could be scaled to 25nm node in a 3D array, providing density far beyond conventional 2D NAND Flash.

Macronix has invested in 3D memory study for a number of years already. In 2006, Macronix presented its first 3D NAND Flash technical paper in the Symposium on VLSI Technology in Honolulu, Hawaii (also the first published work on 3D NAND Flash, concomitant with another 3D NAND Flash work from another leading edge company in the same conference). Since then, Macronix has announced its research work in 3D memories continuously in VLSI Symposium, IEDM (IEEE International Electron Devices Meeting) and IMW (IEEE International Memory Workshop) and has become one of the world’s leading researchers in 3D technology.

Two technical papers from Macronix have been presented in the 2010 Symposium on VLSI Technology held in Honolulu June 15-17. In addition to the highlight paper addressing 3D NAND Flash (Paper 12.4  A Highly Scalable 8-Layer 3D Vertical-Gate (VG) TFT NAND Flash Using Junction-Free Buried Channel BE-SONOS Device, Hang-Ting Lue, et al.), a paper discussing ReRAM technology (Paer 8.4  A Novel TiTe Buffered Cu-GeSbTe/SiO2 Electrochemical Resistive Memory (ReRAM), Y.-Y. Lin, et al.) has also been chosen.

The Symposium on VLSI Technology was established in 1982 and it has since become the world’s premier forum for the presentation of advances in the VLSI (Very-large-scale integration) technology. Usually there are about 90 research papers selected from over 200 submissions for the annual discussion. Macronix’s research is the only work from Taiwan selected as a highlight paper this year. In 2009, another paper from Macronix (A Novel Buried-Channel FinFET BE-SONOS NAND Flash with Improved Memory Window and Cycling Endurance) was also highlighted by VLSI Symposium.

Macronix’s research works in advanced non-volatile memory technology has attracted much international attention. Several other technical papers have also been highlighted by international conferences in recent years are shown as below:

• High-Speed Multilevel Resistive RAM Using RTO WOx (2009, Solid State Devices and Materials Symposium, SSDM)
• The Bridge Structure for Advanced Phase Change Memory Investigations(2008, European Symposium on Phase Change and Ovonic Science, EPCOS)
• Ultra-Thin Phase-Change Bridge Memory Device Using GeSb (2006, IEDM). This joint research paper with IBM & Qimonda (Macronix as first author) was selected as a very significant paper by IEDM and was invited to present at The International Solid-State Circuits Conference (ISSCC) in 2007.
• Scaling Properties of Phase Change Nanostructures and Thin Films (2006 EPCOS).