Faraday Launches USB 3.0 PHY in UMC 0.13um

Faraday Technology Corporation announced the availability of the commercial USB 3.0 physical layer (PHY) at UMC 0.13um high-speed (HS) process. This new component is based upon USB 3.0 version 1.0 specification, functionally and electrically, with the maximum speed of 5.0Gbps.

Succeeding to the successful histories on USB 2.0, Faraday’s USB 3.0 PHY is one of the earliest solutions appearing in the market. Due to the demand of higher-speed peripheral interface evoked by the widening gap between the speed limitation of USB 2.0 and increasing growth of data capacity; the application of USB 3.0 (SuperSpeed USB) will cover not only the territories of its predecessor also some new areas created by this high-speed transmission, especially in multimedia storage. Faraday has been engaged by numerous customers for product development, including one host controller provider. Faraday expects this will bring her great opportunity after the application booming in 2010.

"Just weeks after launching the leading PCIe GII solution, now Faraday has the USB 3.0PHY, which points to the fact that Faraday do have the most robust design capabilities in high-speed IO among the peers," said Steve Wang, Chief Strategy Officer at Faraday. "As a contributor to the USB Implementers Forum (USB-IF), Faraday has been dedicated to USB 3.0 development in order to deliver early products right after the specification’s finalization. We have a clear roadmap ahead and the achievement is satisfying so far. Following the 0.13um PHY, the 90nm PHY will be available soon, and 55nm and 40nm are under development as well. Faraday is optimistic in USB 3.0’s prevalence and confident with our ability to provide the most competitive USB 3.0 solution and service," he added.

"We are pleased to see that a USB 3.0 PHY solution has been made available from Faraday," said Jeff Ravencraft, USB-IF president and chairman. "The market is ready for SuperSpeed USB technology to meet the increasing demand for faster transfer speeds. USB 3.0 PHY solutions like Faraday’s will help enable the industry to bring SuperSpeed USB products to the market."

To achieve the specification with trade-off between power and die size, Faraday has carried out some sophisticated improvement in this PHY architecture, including a new compensation circuits in the equalizer of receiver to eliminate the channel loss caused by the cable and trace wire in the board. Some other new architectures also work for clock data recovery and transmitter to make the eye diagram meet the specification in all conditions.

At the upcoming SuperSpeed USB Developers Conference (5/20-5/21, Tokyo, JP), Faraday will demo the complete USB 3.0 solutions, covering host solution (USB 3.0-PCIe) on PC, device platforms for SSD development, and USB 3.0-SATA bridge chip.