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NXGN Data Assigned Two Patents

Performing efficient searches and queries in storage node, programmable data write management for operating same inSSD

Performing efficient searches and queries in storage node
NXGN Data, Inc., Irvine, CA,
has been assigned a patent (9,092,321) developed by Salessi, Nader, Irvine, CA, for a “system and method for performing efficient searches and queries in a storage node.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system and method of providing enhanced data processing and analysis in a storage node, such as a solid state drive, (SSD). The SSD includes flash memory and an SSD processing unit capable of executing searches and analysis on the data in the flash memory without returning all of the data to be searched to a host CPU outside of the SSD. Other processing capabilities incorporated into the SSD may include encryption and decryption, compression and decompression, and in-line indexing of data, and data analytics.

The patent application was filed on July 24, 2013 (13/949,913).

Programmable data write management system and method for operating the same in SSD
NXGN Data, Inc., Irvine, CA,
has been assigned a patent (9,092,362) developed by Alcantara, Joao, Irvine, CA, and Alves, Vladimir, Tustin, CA, for a “programmable data write management system and method for operating the same in a solid state drive.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of writing host data to a storage device including a central processing unit, CPU, a self-organized fast release buffer, FRB, and a non-volatile memory, the storage device being in communication with a host, the method including receiving a command to write the host data to the non-volatile memory from the CPU, the host data being associated with a logical block number, LBN, allocating space in a buffer memory of the FRB for storage of the host data, organizing the host data into one or more codewords, CWs, storing the one or more CWs into the allocated space in the buffer memory, transferring the one or more CWs from the buffer memory to a physical address in the non-volatile memory, and sending the LBN and the physical address to the CPU to update a logical-to-physical table.

The patent application was filed on March 13, 2014 (14/210,020).

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