Skyera/Western Digital Assigned Four Patents

Routing information in non-volatile memory-based storage device
Skyera, LLC, San Jose, CA, acquired by Western Digital Corp. and included in HGST, Inc., has been assigned a patent (9,229,855) developed by Danilak, Radoslav, Cupertino, CA, and Radke, William, Los Gatos, CA, for a “apparatus and method for routing information in a non-volatile memory-based storage device.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory, NVM) blades comprising the non-volatile memory, (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium.“

The patent application was filed on November 12, 2013 (14/078,302).

Atomic write command support in SSD
Western Digital Technologies, Inc., Irvine, CA and Skyera, LLC, San Jose, CA, has been assigned a patent (9,218,279) developed by Tomlin, Andrew J., San Jose, CA, Jones, Justin, Burlingame, CA, and Mullendore, Rodney N., San Jose, CA, for a “atomic write command support in a solid state drive.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of performing an atomic write command in a data storage device comprising a volatile memory and a plurality of non-volatile memory devices configured to store a plurality of physical pages. The method may comprise storing data in a plurality of logical pages, (L-Pages), each associated with a logical address. A logical-to-physical address translation map may be maintained in the volatile memory, and may be configured to enable determination of a physical location, within one or more of the physical pages, of the data referenced by each logical address. The data specified by a received atomic write command may be stored one or more L-Pages. Updates to the entry or entries in the translation map associated with the L-Page(s) storing the data specified by the atomic write command may be deferred until all L-Pages storing data specified by the atomic write command have been written in a power-safe manner.“

The patent application was filed on May 15, 2013 (13/895,016).

Avoiding lower page corruption in storage devices
Western Digital Technologies, Inc., Irvine, CA and Skyera, LLC, San Jose, CA, has been assigned a patent (9,177,638) developed by Danilak, Radoslav, Cupertino, CA, Mullendore, Rodney N., Tomlin, Andrew J., San Jose, CA, Jones, Justin, Burlingame, CA, and Yang, Jui-Yao, San Jose, CA, for a “methods and devices for avoiding lower page corruption in data storage devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device may comprise a plurality of Multi-Level Cell, (MLC) non-volatile memory devices comprising a plurality of lower pages and a corresponding plurality of higher-order pages. A controller may be configured to write data to and read data from the plurality of lower pages and the corresponding plurality of higher-order pages. A buffer may be coupled to the controller, which may be configured to accumulate data to be written to the MLC non-volatile memory devices, allocate space in the buffer and write the accumulated data to the allocated space. At least a portion of the accumulated data may be written in a lower page of the MLC non-volatile memory devices and the space in the buffer that stores data written to the lower page may be de-allocated when all higher-order pages corresponding to the lower page have been written in the MLC non-volatile memory devices.“

The patent application was filed on November 13, 2012 (13/675,913).

Early de-allocation of write buffer in SSD
Western Digital Technologies, Inc., Irvine, CA and Skyera, LLC, San Jose, CA, has been assigned a patent (9,170,939) developed by Jones, Justin, Burlingame, CA, Tomlin, Andrew J., Mullendore, Rodney N., San Jose, CA, and Danilak, Radoslav, Cupertino, CA, for a “early de-allocation of write buffer in an SSD.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage system includes: non-volatile solid state memory including non-volatile storage units and a temporary register, a data storage controller configured to receive a write command including a plurality of logical segments of data from a host, a write buffer allocated to receive a portion of the plurality of logical segments of data and accumulate a physical segment of data corresponding to a write unit of the solid state memory, a solid state memory controller configured to transmit the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical segment of data. The data storage controller acknowledges completion of the write command to the host after the last logical segment of data is written to the write buffer, and deallocates the write buffer after the solid state memory completes reception of the accumulated data into the temporary storage register.“

The patent application was filed on November 26, 2013 (14/090,596).