SanDisk Assigned Eight Patents

Intelligent bit recovery for flash memory
SanDisk Enterprise IP LLC, Milpitas, CA, has been assigned a patent (8,910,020) developped by Frayer Jack Edward, Boulder Creek, CA, Olbrich Aaron Keith, Morgan Hill, CA, Stonelake Paul Roger, Santa Clara, CA, Kulkarni Anand Krishnamurthi, San Jose, CA, and  Ma Yale Yueh, Palo Alto, CA, for a “intelligent bit recovery for flash memory”.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method and system for intelligent bit recovery identifies toggling bits, which change in value from one read to the next, and examines a subset of potential bit patterns. The subset is a fraction of the potential bit patterns, and is based on an understanding of the flash memory and the problems that may cause the toggling bits. The intelligent bit recovery may analyze at least one aspect of the flash memory to identify a problem, or plurality of problems, that is potentially causing the toggling bits, and to select the subset of potential bit patterns as potential solutions. The subset of potential bit patterns examined by the intelligent bit recovery is a small fraction of the entire set of potential bit patterns.“

The patent application was filed on October 31, 2011 (13/285,873).

Flash memory with random partition
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,910,017) developped by Sharon Eran, Rishon Lezion, Israel, and Alrod Idan, Herzliya, Israel, for a “flash memory with random partition”.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and method for partitioning data in long term memory of a flash memory device is disclosed. The method may include the steps of identifying a type of data that has been received and routing the data to one of at least two partitions in the long term memory array. One partition of the flash memory device may be optimized for random data while another is optimized for sequential data. The method includes identifying the type of data and routing the data to the appropriate partition. Data may be analyzed and routed upon receipt or initially stored in a default partition and later analyzed and routed to another partition. The partition for random data may be configured for storing data using a first level of ECC protection while the second may be configured for storing data using a second, stronger level of ECC protection.”

The patent application was filed on October 31, 2011 (13/539,969).

Detecting copyback programming problems
SanDisk Enterprise IP LLC, Milpitas, CA, has been assigned a patent (8,909,982) developped by Weston-Lewis Graeme Moffat, Fremont, CA, Prins Douglas Alan, Laguna Hills, CA, Olbrich Aaron Keith, Morgan Hill, CA for a “system and method for detecting copyback programming problems.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and systems are disclosed herein for detecting problems related to copyback programming. After the copyback data is read into the internal flash buffer, a part of the copyback data stored in the internal flash buffer (such as spare data) is analyzed to determine whether there are any errors in a part of the copyback data read. The analysis may be used by the flash memory in one or more ways related to the current copyback operation, subsequent copyback operations, subsequent treatment of the data in the current copyback operation, and subsequent treatment of the section in memory associated with the source page.”

The patent application was filed on October 31, 2011 (13/285,892).

Compensation for sub-block erase
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,909,493) developped by Avila Chris, Saratoga, CA, Dong Yingda, San Jose, CA, and Mui Man Lung, Fremont, CA, for a “compensation for sub-block erase .”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme. “

The patent application was filed on May 15, 2014 (14/279,037).

Erase for 3D non-volatile memory with sequential selection of word lines
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,908,444) developped by Costa Xiying, San Jose, CA, Yu Seung, San Ramon, CA, Scheuerlein Roy E., Cupertino, CA, and Li Haibo, Sunnyvale, CA, and Mui Man L., Santa Clara, CA, for a “erase for 3D non-volatile memory with sequential selection of word lines.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element’s distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.”

The patent application was filed on August 6, 2013 (13/960,360).

Storage device and method for performing self-refresh operation
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,908,443) developped by Ellis Robert W., Phoenix, AZ, for a “storage device and method for performing a self-refresh operation.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device and method for performing a self-refresh operation are disclosed. In one embodiment, a storage device determines that the self-refresh operation needs to be performed. In response to that determination, the storage device performs the self-refresh operation by reading data from the memory and writing the data back to the memory without transferring the data outside of the storage device.”

The patent application was filed on May 27, 2014 (14/287,988).

Double verify method in multi-pass programming to suppress read noise
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,908,441) developped by Dutta Deepanshu, Santa Clara, CA, Oowada Ken, Fujisawa, Japan, Sano Genki, Kanagawa, Japan, and Higashitani Masaaki, Cupertino, CA, for “double verify method in multi-pass programming to suppress read noise.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Memory cells which have read noise are identified during a programming pass and an amount of programming is increased for noisy memory cells compared to non-noisy cells. The read noise is indicated by a decrease in the threshold voltage of a cell when the cell is repeatedly read. In one approach, during the programming pass, a cell enters a temporary lockout state when it passes a first verify test and is subject to one or more additional verify tests. Data is stored to identify the cell as a noisy cell or a non-noisy cell based on the one or more additional verify tests. Or, the cells are subject to the one or more additional verify tests at the end of the programming pass. In a subsequent programming pass, the noisy cell is programmed using a stricter verify condition. Or, the noisy cell is kept in an erased state. “

The patent application was filed on October 15, 2013 (14/053,866).

Erase operation with controlled select gate voltage for 3D non-volatile memory
SanDisk Technologies Inc., Plano, TX, has been assigned a patent (8,908,435) developped by Li Haibo, Sunnyvale, CA, Costa Xiying, and Zhang Chenfeng, San Jose, CA, for “erase operation with controlled select gate voltage for 3D non-volatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles. “

The patent application was filed on December 21, 2011 (13/332,844).