Micron Assigned Five Patents

Flash translation layer
Micron Technology, Inc., Boise, ID, has been assigned a patent (8,838,876) developed by Troy Manning, Meridian, ID, for “solid state storage devices and methods for flash translation layer.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.”

The patent application was filed on Oct. 13, 2008 (12/250,043).

Memory arrays
Micron Technology, Boise, ID, has been assigned a patent (8,829,484) developed by Scott E. Sills, Boise, ID, for “memory arrays.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include methods of forming memory structures. An electrically insulative line is formed over a base. Electrode material is deposited over the line and patterned to form a pair of bottom electrodes along the sidewalls of the line. Programmable material is formed over the bottom electrodes, and a top electrode is formed over the programmable material. The bottom electrodes may each contain at least one segment which extends at angle of from greater than 0 degree. to less than or equal to about 90 degree. relative to a planar topography of the base. Some embodiments include memory structures having a bottom electrode extending upwardly from a conductive contact to a programmable material, with the bottom electrode having a thickness of less than or equal to about 10 nanometers. Some embodiments include memory arrays and methods of forming memory arrays. “

The patent application was filed on Aug. 26, 2013 (14/010,243).

Non-volatile memory with resistive access component
Micron Technology, Boise, ID, has been assigned a patent (8,830,738) developed by two co-inventors for a “non-volatile memory with resistive access component.”

The co-inventors are Jun Liu, and Michael P. Violette, Boise, ID.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include apparatus and methods having a memory element configured to store information and an access component configured to allow conduction of current through the memory element when a first voltage difference in a first direction across the memory element and the access component exceeds a first voltage value and to prevent conduction of current through the memory element when a second voltage difference in a second direction across the memory element and the access component exceeds a second voltage value, wherein the access component includes a material excluding silicon.”

The patent application was filed on Feb. 4, 2013 (13/758,644).

SSD controller with expansion mode
Micron Technology, Boise, ID, has been assigned a patent (8,832,392) developed by Dean Klein, Eagle, ID, for a “solid state storage device controller with expansion mode.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Solid state storage device controllers, solid state storage devices, and methods for operation of solid state storage device controllers are disclosed. In one such solid state storage device, the controller can operate in either an expansion DRAM mode or a non-volatile memory mode. In the DRAM expansion mode, one or more of the memory communication channels normally used to communicate with non-volatile memory devices is used to communicate with an expansion DRAM device.”

The patent application was filed on May 24, 2013 (13/901,806).

Local self-boost using plurality of cut-off cells on single side of string of memory cell
Micron Technology, Boise, Idaho, has been assigned a patent (8,830,775) developed by three co-inventors for a “local self-boost using a plurality of cut-off cells on a single side of a string of memory cells.”

The co-inventors are Ryan G. Fisher, Boise, ID, Koji Sakui, Tokyo, Japan, and Yasushi Matsuyama, Yokohama, Japan.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods for local self-boost of a selected memory cell channel, memory devices, and systems are disclosed. One such method generates a cut-off channel under each of a plurality of memory cells on one of either a source side or a drain side of a selected memory cell.”

The patent application was filed on March 7, 2012 (13/413,762).