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Intermolecular, Toshiba and SanDisk Assigned Three Patents

Nonvolatile memory device, multi-level memory array

Nonvolatile memory device having current limiting element
Intermolecular, Inc., San Jose, CA, Kabushiki Kaisha Toshiba, Tokyo, Japan, and SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (8,995,172) developed by Wang, Yun, San Jose, CA, Chiang, Tony P., Campbell, CA, and Hashim, Imran, Saratoga, CA, for a “nonvolatile memory device having a current limiting element.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps, i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

The patent application was filed on February 21, 2014 (14/186,726).

Multi-level memory array having resistive elements for multi-bit data storage
Intermolecular, Inc., San Jose, CA, Kabushiki Kaisha Toshiba, Tokyo, Japan, and SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (8,995,166) developed by Pramanik, Dipankar, Saratoga, CA, Lazovsky, David E, Los Gatos, CA, Minvielle, Tim, San Jose, CA, and Yamaguchi, Takeshi, Kanagawa, Japan, for a “multi-level memory array having resistive elements for multi-bit data storage.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A resistor array for multi-bit data storage without the need to increase the size of a memory chip or scale down the feature size of a memory cell contained within the memory chip is provided. The resistor array incorporates a number of discrete resistive elements to be selectively connected, in different series combinations, to at least one memory cell or memory device. In one configuration, by connecting each memory cell or device with at least one resistor array, a resistive switching layer found in the resistive switching memory element of the connected memory device is capable of being at multiple resistance states for storing multiple bits of digital information. During device programming operations, when a desired series combination of the resistive elements within the resistor array is selected, the resistive switching layer in the connected memory device can be in a desired resistance state.

The patent application was filed on December 20, 2012 (13/721,279).

Memory device having an integrated two-terminal current limiting resistor
Intermolecular, Inc., San Jose, CA, Kabushiki Kaisha Toshiba, Tokyo, Japan, and SanDisk 3D LLC, Milpitas, CA, has been assigned a patent (8,987,865) developed by Pramanik, Dipankar, Saratoga, CA, Chiang, Tony P., Campbell, CA, and Lee, Mankoo, Fremont, CA, for a “memory device having an integrated two-terminal current limiting resistor.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

The patent application was filed on May 27, 2014 (14/288,003).

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