Aplus Flash Technology Assigned Three Patents

VSL-based VT-compensation and analog program scheme
for NAND array without CSL
Aplus Flash Technology, Inc., Fremont, CA, has been assigned a patent (9,443,579) developed by Lee, Peter Wung, Saratoga, CA, for a “VSL-based VT-compensation and analog program scheme for NAND array without CSL.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A YUKAI NAND array comprising multiple strings of all TLC and mixed TLC+SLC memory cells associated with hierarchical global/local bit lines, (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line, (LSL) with full BL-shielding without wasting extra silicon area and without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding to perform concurrent ABL, AnP and Alt-WL program under multi-passes program schemes with LBL program voltage compensations and half-BL Odd/Even program-verify and read operations with individual V.sub.SL-based Vt-compensation to mitigate high WL-WL and BL-BL coupling effects.“

The patent application was filed on August 17, 2015 (14/828,427).

NAND array architecture for multiple simultaneous program and read
Aplus Flash Technology, Inc., Fremont, CA, has been assigned a patent (9,443,578) developed by Lee, Peter Wung, Saratoga, CA, for a “NAND array architecture for multiple simultaneous program and read.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This invention discloses a HiNAND array scheme with multiple-level of bit lines, (BLs) including metal3 global bit lines, GBLs, divided metal2 Segment bit lines, SBLs, and divided metal1 block bit lines, BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.“

The patent application was filed on December 27, 2015 (14/979,458).

NAND array architecture for multiple simutaneous program and read
Aplus Flash Technology, Inc., Fremont, CA, has been assigned a patent (9,437,306) developed by Lee, Peter Wung, Saratoga, CA, for a “NAND array architecture for multiple simultaneous program and read.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This invention discloses a HiNAND array scheme with multiple-level of bit lines, (BLs) including metal3 global bit lines, (GBLs), divided metal2 Segment bit lines, SBLs, and divided metal1 block bit lines, (BBLs) laid out in parallel to each other respectively for a plurality of NAND Strings. All other source lines or power lines connected to bottoms of corresponding String capacitances of GBLs, SBLs, and BBLs are associated with metal0 line laid out perpendicular to those BLs. Under the HiNAND array scheme, conventional one-WL Read and Program-Verify operations are replaced by multiple-WL and All-BL Read and Program-Verify operations executed with charge capacitance of SBLs being reduced to 1/10- 1/20 of capacitance of GBLs to achieve DRAM-like faster operation, less operation stress, and lower power consumption. A preferred set of program biased voltages on the selected WL and remaining non-selected WLs associated with a Multiplier and a DRAM-like charge-sharing Latch Sensing Amplifier is proposed.“

The patent application was filed on December 27, 2015 (14/979,459).