Micron Assigned Seven Patents

Memory cell architecture for multilevel cell programming
Micron technology, Inc., Boise, ID, has been assigned a patent (9,607,691) developed by Allegra, Mario, Milan, Italy, and Boniardi, Mattia, Cormano, Italy, for a “memory cell architecture for multilevel cell programming.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states–e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.“

The patent application was filed on February 17, 2016 (15/046,330).

Three dimensional memory array architecture
Micron technology, Inc., Boise, ID, has been assigned a patent (9,595,667) developed by Pio, Federico, Brugherio, Italy, for a “three dimensional memory array architecture.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Three dimension memory arrays and methods of forming the same are provided. An example three dimension memory array can include a stack comprising a plurality of first conductive lines separated from one another by at least an insulation material, and at least one conductive extension arranged to extend substantially perpendicular to the plurality of first conductive lines, such that the at least one conductive extension intersects a portion of at least one of the plurality of first conductive lines. Storage element material is formed around the at least one conductive extension. Cell select material is formed around the at least one conductive extension.“

The patent application was filed on February 1, 2016 (15/011,816).

Data streaming for solid-state bulk storage devices
Micron technology, Inc., Boise, ID, has been assigned a patent (9,575,674) developed by Chen, Frank, North Potomac, MD, and Rong, Yuan, Shanghai, China, for a “data streaming for solid-state bulk storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods facilitate data streaming in bulk storage devices by generating linked lists containing entries for both user data and metadata. These linked lists containing mixed data types facilitate receiving and outputting user data, and to insert or ignore, respectively, metadata corresponding to that user data without interrupting flow of the user data.“

The patent application was filed on January 5, 2015 (14/589,382).

Persistent content in nonvolatile memory
Micron technology, Inc., Boise, ID, has been assigned a patent (9,563,554) developed by Hulbert, Jared E., Shingle Springs, CA, Rudelic, John C., Folsom, CA, and Wang, Hongyu, Shanghai, China, for a “persistent content in nonvolatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Applications may request persistent storage in nonvolatile memory. The persistent storage is maintained across power events and application instantiations. Persistent storage may be maintained by systems with or without memory management units.“

The patent application was filed on September 8, 2015 (14/848,159).

Assigning addresses to memory devices
Micron technology, Inc., Boise, ID, has been assigned a patent (9,552,311) developed by Norman, Robert D., San Jose, CA, and Lakhani, Vinod C., Milpitas, CA, for a “method for assigning addresses to memory devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.“

The patent application was filed on June 2, 2014 (14/293,822).

Smart storage device
Micron technology, Inc., Boise, ID, has been assigned a patent (9,529,734) developed by Asnaashari, Mehdi, Danville, CA, and Victor, Tsai, Palo Alto, CA, for a “smart storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A smart storage device can have a smart-card portion with access control circuitry and integrated memory, a controller in selective communication with the smart-card portion, and a memory device in communication with the controller. The memory device can be separate from the smart-card portion and can store one or more smart-card applications.“

The patent application was filed on October 3, 2014 (14/506,031).

Memory cells
Micron technology, Inc., Boise, ID, has been assigned a patent (9,515,261) developed by Sandhu, Gurtej S., and Pandey, Sumeet C., Boise, ID, for a “memory cells and methods of making memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.“

The patent application was filed on March 25, 2016 (15/080,802).