Synopsys Assigned Three Patents

Data storage element and signal processing
Synopsys, Inc., Mountain View, CA, has been assigned a patent (9,602,085) developed by Dubey, Prashant, Uttar Pradesh, India, Mittal, Shivangi, Delhi, India, and Jha, Raushan Kumar, Uttar Pradesh, India, for a “data storage element and signal processing method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data storage element comprises a master stage, (MS) with a first and a second latch, LI, L2, an error stage, (ES) and a slave stage, (SLS). The first latch, (LI) generates in a clocked fashion based on a clock signal, (CLK, CLKT, CLKB) a first logical signal, (DOUT1) based on an input signal, (DATA) in relation to a first threshold level, (TP1). The second latch generates, (L2) in a clocked fashion based on the clock signal, (CLK, CLKT, CLKB) a second logical signal, (DOUT2) based on the input signal, (DATA) in relation to a second threshold level, (TP2). The second threshold level, (TP2) is distinct from the first threshold level, (TP1). The error stage provides an error signal, (ER) with a first logical state if the first and the second logical signal, (DOUT1 , DOUT2) have the same logical state, and with a second logical state they have different logical states. The slave stage, (SLS) sets an output value, (Q) of the data storage element to a common logical state of the first and the second logical signal, (DOUT1 , DOUT2) when the error signal, (ER) has the first logical state, and keeps the output value, (Q) unchanged otherwise.“

The patent application was filed on November 7, 2013 (14/894,323).

Floating gate non-volatile memory bit cell
Synopsys, Inc., Mountain View, CA, has been assigned a patent (9,601,203) developed by Hommelgaard, Mads, Kirkland, WA, Horch, Andrew, and Niset, Martin, Seattle, WA, for a “floating gate non-volatile memory bit cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A solid-state non-volatile memory, (NVM) device includes a memory bit cell. The memory bit cell includes a field effect transistor, (FET) fabricated on a substrate and having a floating gate. The floating gate includes a thick oxide layer. The FET includes drain and source, each fabricated within the substrate and coupled to the floating gate and a channel region with native doping. The drain is fabricated to have a halo region. A method for fabricating a solid-state NVM device includes fabricating solid state device including NVM bit cell which provides multiple storage and includes an FET on substrate. The method also includes fabricating floating gate of the FET including thick gate oxide layer, and fabricating drain and source of FET within the substrate, drain and source coupled to the floating gate and channel region with native doping. Further, the method includes fabricating halo region within the substrate at the drain.“

The patent application was filed on June 9, 2012 (13/492,811).

NVM device using FN tunneling with parallel powered source and drain
Synopsys, Inc., Mountain View, CA, has been assigned a patent (9,553,207) developed by Horch, Andrew E., Seattle, WA, and Gilliland, Troy N., Bellevue, WA, for a “NVM device using FN tunneling with parallel powered source and drain.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory, (NVM) bitcell includes a capacitor, a transistor, and a tunneling device. The capacitor, transistor, and tunneling device are each electrically coupled to different active regions and metal contacts. The three devices are coupled by a floating gate that traverses the three active regions. The tunneling device is used to program and erase the device, allowing for faster page erasure, and thus allows for rapid testing and verification of functionality. The transistor is used to read the logical state of the floating gate. The capacitor and floating gate are capacitively coupled together, removing the need for a separate selection device to perform read, write, and/or erase operations.“

The patent application was filed on September 25, 2013 (14/036,249 ).