Microchip's disaggregated architecture leverages host CPU and PCIe infrastructure to overcome traditional storage bottlenecks
FusIOnX powers multi-agent collaboration, context retention, and scalable deployment
Seamless compatibility between XConn's next-gen CXL 3.1 switch and ScaleFlux MC500 CXL 3.1 Type 3 memory controller
Offers support for up to 32 E3.S PCIe Gen 5 NVMe dual-port SSD and designed for peak performance, HA and easy scalability
Including F2026 server configured with 26 ScaleFlux CSD 5000 NVMe SSDs and 4 NVIDIA BlueField-3 DPUs, EB202-CP-LLM platform and Unigen's upcoming AI inference modules, and PCIe Gen6 high-density AI storage solution with H3 Platform
Ready for All Customers, the platform helps enterprises expand memory, optimize performance, and reduce costs - all with simplicity and flexibility
And with presentations of Pete Kirkpatrick, chief architect, Svitlana Tumanova, technical director, and John “Coz” Colgrove, founder and chief visionary officer
Supports wide range of HBM versions, including HBM2E, HBM3, HBM3E, HBM4, and HBM4E
Including members’ presentations and demos
Enabling new capabilities for AI, cloud, enterprise, and client storage
With sponsored presentation session - UALink 200G 1.0 specification overview and applications and open standards pavilion kiosk
Reducing drastically infrastructure costs
To transform and power its legal analytics platform with SupremeRAID in less than 6 months
Authors propose the Probability-Sensitive Wear Leveling (PS-WL) scheme, which shifts optimization goal from balancing wear to directly balancing failure risk.
Protocol-aware provisioning of resource over CXL fabrics
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