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Smart Storage/SanDisk Assigned Four Patents

Electronic system with storage drive life estimation mechanism and method, storage control system with power down mechanism and method of operation thereof, storage system with data transfer rate adjustment for power throttling, storage control system with erase block mechanism and method of operation

Electronic system with storage drive life estimation mechanism
Smart Storage Systems, Inc., (acquired by SanDisk Corporation), Milpitas, CA, has been assigned a patent (9,361,222) developed by Fitzpatrick, James, Sudbury, MA, Dancho, Mark, Chandler, AZ, Higgins, James M., Chandler, AZ, and Kresse, James M., Gilbert, AZ, for a “electronic system with storage drive life estimation mechanism and method of operation thereof.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, methods and/or devices are used to enable storage drive life estimation. In one aspect, the method includes, (1) determining two or more age criteria of a storage drive, and, (2) determining a drive age of the storage drive in accordance with the two or more age criteria of the storage drive.

The patent application was filed on July 17, 2014 (14/334,324).

Storage control system with power down mechanism
Smart Storage Systems, Inc., (acquired by SanDisk Corporation), Milpitas, CA, has been assigned a patent (9,298,252) developed by Ellis, Robert W., Phoenix, AZ, Virgin, Theron Wayne, and Creasman, Scott, Gilbert, AZ, for a “storage control system with power down mechanism and method of operation thereof.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage control system and method of operation thereof includes: a control unit for initiating a hardening process beginning at a power-down signal, a counter module, coupled to the control unit for tracking a recorded time beginning at the power-down signal, a completion module, coupled to the counter module, for generating a work-complete entry in memory devices at a conclusion of the hardening process, and a calculation module, coupled to the completion module, for calculating a power down margin by determining the recorded time between the work-complete entry and a complete power loss of a hold-up power.

The patent application was filed on April 2, 2013 (13/855,567).

Storage system with data transfer rate adjustment for power throttling
Smart Storage Systems, Inc., (acquired by SanDisk Corporation), Milpitas, CA, has been assigned a patent (9,244,519) developed by Ellis, Robert W., Phoenix, AZ, DelPapa, Kenneth B., Madison, WI, and Lucas, Gregg S., Tucson, AZ, for a “storage system with data transfer rate adjustment for power throttling.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A storage control system, and a method of operation thereof, including: a host interface unit for receiving a host command from a host system, a power measurement hardware, coupled to the host interface unit, for reading a current value of electrical power supplied by the host system in response to the host command, and a power monitor controller, coupled to the power measurement hardware, for adjusting a bus speed for controlling data transfer through a channel shared by a number of non-volatile memory devices, the bus speed is adjusted based on the current value of the electrical power.

The patent application was filed on June 25, 2013 (13/926,900).

Storage control system with erase block mechanism
Smart Storage Systems, Inc., (acquired by SanDisk Corporation), Milpitas, CA, has been assigned a patent (9,239,781) developed by Jones, Ryan, Mesa, AZ, and Ellis, Robert W., Phoenix, AZ, for a “storage control system with erase block mechanism and method of operation thereof.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of operation of a storage control system includes: partitioning memory channels with memory devices, selecting a super device with one of the memory devices from one of the memory channels, the super device having a super chip select connected to chip selects of the memory devices, and selecting a super block associated with the super device.

The patent application was filed on October 10, 2012 (13/648,869)

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