Xilinx Announces Low-Density Parity-Check Error Correction IP Fundamental

Xilinx, Inc. announced its Low-Density Parity-Check (LDPC) error correction IP fundamental to enabling next generation flash-based applications for the cloud and data center storage market.

As NAND flash continues to advance with 3D NAND technologies, LDPC error correction is a critical core function for meeting the reliability and endurance requirements of today’s storage solutions.

LDPC IP solution features code performance near Shannon limit, achieves low error floor, and supports both hard and soft decision decoding. The architecture is scalable and future proof to support various next-generation non-volatile memory devices and offers the high throughput and low latency required for the most demanding storage applications. This solution requires 50% less logic versus alternate solutions and is Xilinx FPGA optimized for smaller area and power.

“Xilinx has leveraged over a decade of error correction, DSP, and LDPC expertise to deliver a world-class LDPC solution for the data center storage market and is currently the only FPGA vendor to do so,” said Dr. Chris Dick, Xilinx chief DSP architect. “We’ve optimized the feature set of the LDPC IP to address the unique characteristics of flash and meet the cloud’s most demanding storage requirements.”

The flash memory LDPC Error Correction LogiCORE IP is available for early access with availability to begin in Q4 2015.