Taiwan Semiconductor Manufacturing Assigned Two Patents

Concurrent operation of plural flash memories
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, Taiwan, has been assigned a patent (9,047,956) developed by Yang, Tien-Chun, San Jose, CA, Lee, Chia-Fu, and Chih, Yue-Der, Hsin-Chu, Taiwan, for a “concurrent operation of plural flash memories.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.“

The patent application was filed on August 30, 2013 (14/014,471).

Validating stacked dies by comparing connections
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, Taiwan, has been assigned a patent (9,047,432) developed by Mehta, Ashok, Los Gatos, CA, John, Stanley, Fremont, CA, Ting, Kai-Yuan, Goel, Sandeep Kumar, San Jose, CA, and Yeh, Chao-Yang, Luzhou, Taiwan, for a “system and method for validating stacked dies by comparing connections.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A system comprises a processor-implemented tool configured to generate a layout of an integrated circuit, (IC) die. At least one non-transitory machine readable storage medium includes a first portion encoded with a first gate-level description of first and second circuit patterns to be formed on first and second integrated circuit, (IC) dies, respectively, and a second portion encoded with a second gate level description of the first and second circuit patterns received from the processor implemented tool. The second gate level description includes power and ground ports, and the first gate level description does not include power and ground ports. A processor-implemented first verification module is provided for comparing the first and second gate level descriptions and outputting a verified second gate-level description of the first and second circuit patterns.“

The patent application was filed on February 19, 2013 (13/770,158).