Silicon Motion Assigned two Patents

Accessing flash memory and associated flash memory controller
Silicon Motion, Inc., Jhubei, Taiwan, has been assigned a patent (8,984,373) developed by Yang, Tsung-Chieh, Hsinchu, Taiwan, for a “method for accessing flash memory and associated flash memory controller.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”An exemplary method for accessing a flash memory. The method comprising obtaining a first random sequence, utilizing the first random sequence as a first seed for generating a second random sequence, wherein the first random sequence is not equivalent to the second random sequence, scrambling data according to the second random sequence for generating scrambled data, performing an error correction encoding operation upon the first random sequence and the scrambled data for generating parity check code, and storing the scrambled data and the parity check code to the flash memory.“

The patent application was filed on February 22, 2012 (13/402,596).

Data storage device and flash memory control method
Silicon Motion, Inc., Jhubei, Hsinchu County, Taiwan, has been assigned a patent (8,984,171) developed by Ke, Kuan-Yu, Jhubei, Taiwan, for a “data storage device and flash memory control method.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A data storage device and a flash memory control method with a cache space. The flash memory control method includes the following steps: using a plurality of channels to access a flash memory, wherein the flash memory has a plurality of blocks each with a plurality of pages, and the blocks are grouped to be accessed by the different channels, allocating a random access memory to provide a cache space, the cache space having a plurality of cache areas caching write data for the different channels, respectively, distributing the data issued from a host to correspond to the different channels, and reusing a latest-updated cache area of the cache space to cache write data when a logical address requested to be written with data is identical to a logical address that the latest-updated cache area corresponds to.“

The patent application was filed on December 9, 2013 (14/100,627).