Seagate Assigned Five Patents

Cell-to-cell program interference aware data recovery when ECC fails
with optimum read reference voltage
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (9,378,090) developed by Cai, Yu, San Jose, CA, Wu, Yunxiang, Cupertino, CA, and Haratsch, Erich F., San Jose, CA, for a “cell-to-cell program interference aware data recovery when ECC fails with an optimum read reference voltage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to recover data stored in the memory determined to exceed a maximum number of errors after performing a first read operation using a first read reference voltage. The controller may perform a second read operation using a second read reference voltage. The controller may identify a victim cell having a threshold voltage in a region between the first read reference voltage and the second read reference voltage. The controller may perform a third read operation on aggressor cells of the victim cell. The controller may perform a fourth read operation using the first read reference voltage with bit-fixed values on the victim cell based on a type of interference from the aggressor cells.“

The patent application was filed on June 16, 2014 (14/305,208).

Adaptive read error recovery for memory devices
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (9,397,703) developed by Ghaly, Mai A., Bloomington, MN, and Patapoutian, Ara, Hopkinton, MA, for a “adaptive read error recovery for memory devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Some embodiments involve a method of detecting an error of a memory device. It is determined whether the detected error is a catastrophic error. If it is determined that the error is a catastrophic error, an error recovery process is bypassed. Some aspects involve a method of detecting an error of a memory device. It is determined whether a counter value is above a predetermined value. If it is determined that the counter value is above the predetermined value an error recovery process is bypassed and a redundant parity recovery process is performed.“

The patent application was filed on December 4, 2013 (14/096,752).

NVMHCI attached hybrid data storage
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (9,395,934) developed by Moon, John Edward, Superior, CO, and Kusbel, Paul Francis, Longmont, CO, for a “NVMHCI attached hybrid data storage.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A hybrid data storage device includes a solid-state memory device, a disc-type memory device and a hybrid data storage device controller in communication with the solid-state memory device and the disc-type memory device. The hybrid data storage device controller is configured to receive Non-Volatile Memory Host Controller Interface, (NVMHCI) commands from a host and use logic to make decisions for the optimization and efficient performance of the solid-state memory device and the disc-type memory device.“

The patent application was filed on April 18, 2014 (14/256,500).

Management of and region selection for writes to non-volatile memory
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (9,395,924) developed by Cohen, Earl T, Oakland, CA, and Canepa, Timothy Lawrence, Los Gatos, CA, for a “management of and region selection for writes to non-volatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Management of and region selection for writes to non-volatile memory of an SSD improves performance, reliability, unit cost, and/or development cost of an SSD. A controller receives and determines characteristics of writes, (e.g. by analyzing the write data, the write data source, and/or by receiving a hint) and selects a region based on the determined characteristics and properties of regions of non-volatile memory. For example, a controller receives writes determined to be read-only data and selects regions of non-volatile memory containing cells that are likely to have write failures. By placing read-only data in write failure prone regions, the likelihood of an error is reduced, thus improving reliability. As another example, a controller receives writes hinted to be uncompressible and selects regions of non-volatile memory containing uncompressible data.“

The patent application was filed on January 19, 2014 (14/158,827).

Hybrid memory with associative cache
Seagate Technology LLC, Cupertino, CA, has been assigned a patent (9,390,020) developed by Jannyavula Venkata, Sumanth, Shakopee, MN, for a “hybrid memory with associative cache.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses, host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured map the clusters of host LBAs to clusters of solid state drive, (SSD) LBAs. The SSD LBAs correspond to a memory space of the cache. Mapping of the host LBA clusters to the SSD LBA clusters is fully associative such that any host LBA cluster can be mapped to any SSD LBA cluster.“

The patent application was filed on July 6, 2012 (13/543,079).