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Micron Assigned Two Patents

Forming NAND unit cells, hierarchical memory architecture

Micron Technology, Inc., Boise, ID, has been assigned a patent (8,610,193) developed by D.V. Nirmal Ramaswamy, Boise, ID, for “semiconductor constructions, NAND unit cells, methods of forming semiconductor constructions, and methods of forming NAND unit cells.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.”

The patent application was filed on Feb. 12, 2013 (13/765,643).

Hierarchical memory architecture to connect mass storage devices
Micron Technology, Boise, ID, has been assigned a patent (8,621,148) developed by Sean Eilert, Penryn, CA, for a “hierarchical memory architecture to connect mass storage devices.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A hierarchical memory storage using a concentrator device that is located between a processor and memory storage devices to provide a succession of memory devices and enable attachment of a memory depth to a processor controller with a limited pin count.

The patent application was filed on July 5, 2012 (13/542,236).

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