NVMDurance Assigned Two Patents

Candidate generation for adaptive flash tuning
NVMDurance Limited, Limerick, Great Britain, has been assigned a patent (9,639,284) developed by Ryan, Conor Maurice, Limerick, Ireland, and Sullivan, Joseph, Shannon, Ireland, for a “candidate generation for adaptive flash tuning.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device, (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, ‘test chips’ from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover, (read) test patterns written with different sets of operating parameters over time, (simulating desired retention periods).“

The patent application was filed on June 27, 2016 (15/194,461).

Offline characterization for adaptive flash tuning
NVMDurance Limited, Limerick, Great Britain, has been assigned a patent (9,639,283) developed by Ryan, Conor Maurice, Limerick, Ireland, and Sullivan, Joseph, Shannon, Ireland, for a “offline characterization for adaptive flash tuning.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device, (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, ‘test chips’ from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover, (read) test patterns written with different sets of operating parameters over time, (simulating desired retention periods).“

The patent application was filed on June 27, 2016 (15/194,450).