Phison Assigned Seven Patents

Data reading method, memory controlling circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,607,704) developed by Lin, Wei, Taipei, Taiwan, Wang, Tien-Ching, Kaohsiung, Taiwan, and Lai, Kuo-Hsin, Hsinchu County, Taiwan, for a “data reading method, memory controlling circuit unit and memory storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data reading method is provided. The data reading method includes receiving a read command from a host system, sending a first read command sequence to obtain a first data string from memory cells of a rewritable non-volatile memory module, performing a decoding procedure on the first data string to generate a decoded first data string, and, if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data string from the memory cells, performing a logical operation on the decoded first data string and the second data string to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted first data string as the decoded first data string.“

The patent application was filed on April 9, 2015 (14/682,123).

Memory controlling circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,600,363) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, and Lin, Chang-Guang, Hsinchu County, Taiwan, for a “data accessing method, memory controlling circuit unit and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.“

The patent application was filed on June 11, 2015 (14/736,284).

Storage device
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,585,272) developed by Chen, Chang-Chih, and Chung, Hung-I, Hsinchu County, Taiwan, for a “storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device including a bearing member, a storage unit, and a casing is provided. The casing has a bottom plate, a top plate and a main assembling structure. The bearing member has an interfering portion and a sub-assembling structure. The storage unit has a body with a first surface and a second surface opposite to each other, a limiting portion and a terminal set. Parts of the terminal set and the limiting portion are located at the first surface. The storage unit and the interfering portion are accommodated in the casing. The interfering portion provides interfering force to the limiting portion, and the bottom plate provides a supporting force to the second surface, so that the storage unit is positioned in the casing. The main assembling structure and the sub-assembling are assembled detachably to each other to configure or detach the bearing member and the casing.“

The patent application was filed on March 15, 2013 (13/831,973).

Decoding method, memory storage device and memory control circuit
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,583,217) developed by Lin, Wei, Taipei, Taiwan, Yen, Shao-Wei, Kaohsiung, Taiwan, Lin, Yu-Hsiang, Yunlin County, Taiwan, Lai, Kuo-Hsin, Hsinchu County, Taiwan, for a “decoding method, memory storage device and memory control circuit unit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A decoding method, a memory storage device and a memory control circuit unit are provided, the decoding method includes: reading a plurality of memory cells according to hard decision voltage to obtain hard bit, performing a parity check procedure for the hard bit to obtain a plurality of syndromes, determining whether the hard bit has error according to the syndromes, if the hard bit has the error, updating the hard bit according to channel information of the hard bit and syndrome weight information corresponding to the hard bit.“

The patent application was filed on June 4, 2014 (14/296,383).

Data erasing method, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,582,416) developed by Yeh, Chih-Kang, Kinmen County, Taiwan, for a “data erasing method, memory control circuit unit and memory storage apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data erasing method for a rewritable non-volatile memory module is provided. The method includes receiving a predetermined command for performing on a first logical sub-unit from a host system, marking a first physical programming unit mapped to the first logical sub-unit as being in an invalid data status and recording a mark for a first physical erasing unit that the first physical programming unit belongs to, in response to the predetermined command. The method further includes selecting the first physical erasing unit according to the mark, copying valid data in the first physical erasing unit to a second physical erasing unit gotten from a spare area of the rewritable non-volatile memory module and erasing data stored in the first physical erasing unit.“

The patent application was filed on January 28, 2014 (14/166,815).

Memory control circuit unit, memory storage apparatus and data accessing
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,582,224) developed by Lin, Wei, Taipei, Taiwan, Lai, Kuo-Hsin, Hsinchu County, Taiwan, and Wang, Tien-Ching, Kaohsiung, Taiwan, for a “memory control circuit unit, memory storage apparatus and data accessing method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.“

The patent application was filed on May 4, 2015 (14/702,768).

Memory management method, memory control circuit unit and memory storage
Phison Electronics Corp., Miaoli, Taiwan, has been assigned a patent (9,563,508) developed by Lin, Wei, Taipei, Taiwan, Hsu, Yu-Cheng, Yilan County, Taiwan, Liu, An-Cheng, Taipei, Taiwan, and Lam, Siu-Tung, Hsinchu, Taiwan, for a “memory management method, memory control circuit unit and memory storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure provides a memory management method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes physical programming units, each of which includes multiple bits. The memory management method includes: identifying a first physical programming unit by applying a predetermined read voltage, where the first physical programming unit is identified as in a fully-erased status, identifying a second and a third physical programming units which are programmed before the first physical programming unit, acquiring status data of the second and the third physical programming unit, computing a difference of the status data between the second and the third physical programming unit, if the difference is larger than a threshold, identifying the second physical programming unit as in a program failure status.“

The patent application was filed on April 23, 2015 (14/693,885).