Intel Assigned Fourteen Patents

File retrieval from multiple storage locations
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,607,002) developed by Schmidt, Johannes P., Los Altos Hills, CA, Shen, Kevin, Sunnyvale, CA, and Bailey, James, San Jose, CA, for a “file retrieval from multiple storage locations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In embodiments, apparatuses, methods and storage media are described that are associated with retrieval of a file stored at multiple storage locations, such as a content file. A file retrieving device may receive an identifier of multiple storage locations from which a file may be downloaded, including content delivery networks and distinct storage servers at a particular content delivery network. The decoder may retrieve portions of the file from the different indicated storage locations. The file retrieving device may be configured to assign portion sizes to various storage locations based on a history of bandwidth experienced from the various storage locations. The file retrieving device may be configured to dynamically manage retrieval of portions of the file from the multiple storage locations, such as by re-assigning a slow or stalled portion from one storage location to a faster or underutilized storage locations. Other embodiments may be described and claimed.“

The patent application was filed on December 18, 2013 (14/133,480).

Implementing multi-level memory hierarchy
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,600,416) developed by Ramanujan, Raj K., Federal Way, WA, Agarwal, Rajat, Beaverton, OR, Cheng, Kai, Portland, OR, Polepeddi, Taarinya, London, Great Britain, Raad, Camille C., Folsom, CA, Zimmerman, David J., El Dorado Hills, CA, Swaminathan, Muthukumar P., Folsom, CA, Ziakas, Dimitrios, Hillsboro, OR, Kumar, Mohan J., Aloha, OR, Coury, Bassam N., Dupont, WA, and Hinton, Glenn J., Portland, OR, for a “apparatus and method for implementing a multi-level memory hierarchy.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as ‘far memory.’ Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as ‘near memory.’“

The patent application was filed on September 30, 2011 (13/997,189).

Check data storage devices for transient faults
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,595,349) developed by Raj, Ashok, Portland, OR, Gabor, Ron, Hertzliya, Israel, Shafi, Hisham, Akko, Israel, Kumar, Mohan J., Aloha, OR, and Yigzaw, Theodros, Sherwood, OR, for a “hardware apparatuses and methods to check data storage devices for transient faults.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.“

The patent application was filed on June 25, 2015 (14/751,113).

Compute erasure codes having positive and negative coefficient
exponents to permit data recovery from more than two failed storage units
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,594,634) developed by Gopal, Vinodh, Westborough, MA, and Ozturk, Erdinc, Hillsboro, OR, for a “techniques to efficiently compute erasure codes having positive and negative coefficient exponents to permit data recovery from more than two failed storage units.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Erasure code syndrome computation based on Reed Solomon, (RS) operations in a Galois field to permit reconstruction of data of more than 2 failed storage units. Syndrome computation may be performed with coefficient exponents that consist of -1, 0, and 1. A product xD of a syndrome is computed as a left-shift of data byte D, and selective compensation based on the most significant bit of D. A product x.sup.-1D of a syndrome is computed as a right-shift of data byte D, and selective compensation based on the most significant bit of D. Compensation may include bit-wise XORing shift results with a constant derived from an irreducible polynomial associated with the Galois field. A set of erasure code syndromes may be computed for each of multiple nested arrays of independent storage units. Data reconstruction includes solving coefficients of the syndromes as a Vandermonde matrix.“

The patent application was filed on June 2, 2014 (14/293,791).

Caching and tiering for cloud storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,588,901) developed by Chahal, Sudip, Gold River, CA, Bahra, Husni, Folsom, CA, Wayman, Nigel, Clane, Ireland, Yoshii, Terry, Folsom, CA, Lockwood, Charles, Beaverton, OR, and Healy, Shane, Celbridge, Ireland, for a “caching and tiering for cloud storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device management system to maintain an access history of a plurality of storage blocks of solid state drives, (SSDs) managed by the storage device management system, and automatically configure each of a plurality of storage blocks to operate in cache mode or tier mode, wherein a ratio of storage blocks operating in cache mode and storage blocks operating in tier mode is based on the access history.“

The patent application was filed on March 27, 2015 (14/670,574).

Non-volatile memory sector rotation
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,588,882) developed by Nelson, Scott E., Vancouver, Canada, and Kwok, Zion S., Burnaby, Canada, for a “non-volatile memory sector rotation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a rotation value prior to storage of the one or more sectors in a non-volatile memory device. Logic then rotates the one or more sectors back by the rotation value after reading the one or more sectors from the non-volatile memory device. Furthermore, at least one indirection block, (corresponding to the one or more sectors) is stored in at least two different logical memory pages of the non-volatile memory. Other embodiments are also disclosed and claimed.“

The patent application was filed on December 2, 2013 (14/094,743).

Using reliability information from multiple storage units
and parity storage unit to recover data for failed one of storage units
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,588,841) developed by Lei, Andre, Burnaby, CA, Nelson, Scott, Vancouver, Canada, Kwok, Zion S., Burnaby, Canada, and Motwani, Ravi H., San Diego, CA, for a “using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed one of the storage units. A decoding operation of the codeword is performed in each of the storage units comprising the data storage units other than the target data storage unit and the parity storage unit to produce reliability information. In response to the decoding operation failing for at least one additional failed storage unit comprising the data and/or parity storage units other than the target data storage unit that failed to decode, reliability information is obtained for the data portion of the at least one additional failed storage unit. The reliability information obtained from the storage units other than the target data storage unit is used to produce corrected data for the data unit in the target data storage unit.“

The patent application was filed on September 26, 2014 (14/499,078).

Heterogeneous input/output, using remote direct memory access, and active message
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,582,463) developed by Cheng, Shiow-Wen Wendy, Portland, OR, and Woodruff, Robert J., Banks, OR, for a “heterogeneous input/output, (I/O) using remote direct memory access, (RDMA) and active message.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Methods and apparatus to provide heterogeneous I/O, (Input/Output) using RDMA, (Remote Direct Memory Access) and/or Active Message are described. In an embodiment, information is exchanged between an embedded system and a storage device via a source device. The embedded system and the storage device exchange information over a first link and a second link instead of a third link in response to a transfer rate of the first link, coupled between the embedded system and the source device) being faster than a transfer rate of the second link, (coupled between the source device and the storage device). The third link is capable to directly couple the embedded system and the storage device. Other embodiments are also disclosed and claimed.“

The patent application was filed on December 9, 2014 (14/564,893).

Spin transfer torque based memory elements for programmable device arrays
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,577,641) developed by Raychowdhury, Arijit, Hillsboro, OR, Tschanz, James W., Portland, OR, and De, Vivek, Beaverton, OR, for a “spin transfer torque based memory elements for programmable device arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays, (FPGAs) and Complex Programmable Logic Arrays, (CPLAs) that use high-density Spin Transfer Torque, (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing, (DSP) system-on-chip, (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.“

The patent application was filed on February 4, 2016 (15/016,260).

Accelerated data recovery in storage system
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,575,853) developed by Hands, Jonmichael P., Folsom, CA, for a “accelerated data recovery in a storage system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “One embodiment provides a storage system. The storage system includes storage system control logic to identify at least one target storage device in response to detection of a failed storage device, request a state of a target device logical block address, (LBA) from each of the at least one target storage device, and read data associated with a mapped device LBA from each target storage device and write the data to at least one replacement storage device. Another embodiment provides a storage device. The storage device includes device control logic to determine a state of a target device logical block address, (LBA) in response to a request, a host interface to provide a reply to the request, the reply including a state indicator related to the state of the target device LBA, a map table including a plurality of device LBAs and respective state indicators, and non-volatile memory, (NVM) including data related to at least one mapped LBA.“

The patent application was filed on December 12, 2014 (14/568,417).

Hash map support in storage device
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,569,141) developed by Foong, Annie, Aloha, OR, and Veal, Bryan E., Beaverton, OR, for a “hash map support in a storage device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment, a storage device may include device processing logic. The device processing logic may acquire a command associated with a key-value pair, (KVP). The command may be, for example, a get, set, or delete command. The KVP may include a hash value and an item. The hash value may be a key in the KVP and the item may be a value in the KVP. The device processing logic may translate the acquired command into one or more block-oriented commands which may be executed by the device processing logic to perform various operations on the storage device.“

The patent application was filed on March 28, 2014 (14/228,822).

System to cache sets of tags of off-die cache memory
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,558,120) developed by Rolan, Dyer, Verin, Spain, Hyuseinova, Nevin, Istanbul, Turkey, Cuesta, Blas A., and Cai, Qiong, Barcelona, Spain, for a “method, apparatus and system to cache sets of tags of an off-die cache memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In response to any determination that a tag of the first set is to be stored to the cache of cache tags, all tags of the first set are stored to the first portion. Any storage of tags of the first set to the cache of cache tags includes storage of the tags of the first set to only a first portion of the cache of cache tags. In another embodiment, a replacement table is maintained for use in determining, based on an indicated level of activity for a set of the cache of cache tags, whether the set is to be selected for eviction and replacement of cached tags.“

The patent application was filed on March 27, 2014 (14/227,940).

SATA receiver equalization margin determination/setting
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,552,267) developed by Sim, Chee Keong, Serendah, Malaysia, Ng, Kai Chong, Butterworth, Malaysia, and Hau, Tze Ming, Seremban, Malaysia, for a “SATA receiver equalization margin determination/setting method and apparatus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an apparatus may comprise a BIOS configured to determine, during POST, whether a device is attached to one of the SATA ports, and on determination that a device is attached to one of the SATA ports, further determine whether a receiver equalization margin has been set for the device. Additionally, the BIOS may be configured to perform a DTLE training to dynamically determine and set the receiver equalization margin for the device, on determination that a receiver equalization margin has not been set for the device. Other embodiments may be described and/or claimed.“

The patent application was filed on December 9, 2014 (14/564,869).

Managing cloud storage
Intel Corporation, Santa Clara, CA, has been assigned a patent (9,547,654) developed by Bhardwaj, Rahul M., Bangalore, India, Hassan, Vishwa, Chandler, AZ, Mant, Thomas A., Black, Christian D., Folsom, CA, Sedayao, Jeffrey C., San Jose, CA, Yoshii, Terry H., West Sacramento, CA, Nayshtut, Alex, Gan Yavne, Israel, Breton, Michael S., Folsom, CA, and Devetter, Douglas P., Cameron Park, CA, for a “technology for managing cloud storage.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Described herein is technology for managing cloud storage. In particular, systems, devices and methods for managing cloud storage are described. In some embodiments, management of cloud storage may result in the designation of storage allocated to a first storage pool as obsolete, and the reallocation and/or reclamation of such storage to a second storage pool and/or a general cloud storage pool. Management may occur in accordance with one or more policies.“

The patent application was filed on October 9, 2013 (14/129,453).