STMicroelectronics Assigned Two Patents

Negative voltage management module for address decoder circuit
of non-volatile memory device
STMicroelectronics S.r.l., Agrate Brianza, MB, Italy, has been assigned a patent (9,613,712) developed by Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, Castagna, Giuseppe, Palermo, Italy, and Perroni, Maurizio Francesco, Furnari, Italy, for a “negative voltage management module for an address decoder circuit of a non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An address decoder circuit is designed to address and bias memory cells of a memory array of a non-volatile memory device. The address decoder circuit includes a charge-pump stage configured to generate a boosted negative voltage. A control stage is operatively coupled to the charge-pump stage for controlling switching on/off thereof as a function of a configuration signal that determines the value of the boosted negative voltage. A decoding stage is configured so as to decode address signals received at its input and generate biasing signals for addressing and biasing the memory cells. A negative voltage management module has a regulator stage, designed to receive the boosted negative voltage from the charge-pump stage and generate a regulated negative voltage for the decoding stage, having a lower ripple as compared to the boosted negative voltage generated by the charge-pump stage.“

The patent application was filed on July 16, 2016 (15/212,208).

Dual non-volatile memory cell comprising erase transistor
STMicroelectronics, (Rousset) SAS, Rousset, France, has been assigned a patent (9,613,709) developed by La Rosa, Francesco, Rousset, France, Niel, Stephan, Greasque, France, and Regnier, Arnaud, Les Taillades, France, for a “dual non-volatile memory cell comprising an erase transistor.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.“

The patent application was filed on September 26, 2016 (15/276,462).